# US 2021/0280262 A1 · Memory device and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280262 A1 - Document ID: US20210280262A1 - Status: Published application - Kind: A1 - Application number: 16/995,151 - Filed: 2020-08-17 - Published: 2021-09-09 - Earliest claimed: 2020-03-04 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Min Kyu JEONG - Web page: https://patentgrep.com/patent/US20210280262A1 ## CPC - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 11/5671: {using charge trapping in an insulator} - G11C 2211/5621: Multilevel programming verification - G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant - G11C 2216/20: Suspension of programming or erasing cells in an array in order to read other cells in it - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided herein is a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may be configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells of the plurality of memory cells. The control logic may be configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop of the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells. ## Claims ### Claim 1 A memory device, comprising: a plurality of memory cells; a peripheral circuit configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells among the plurality of memory cells; and a control logic configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop among the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein, when the suspend command is received during the program pulse apply operation of the n-th program loop, the control logic controls the peripheral circuit to suspend the n-th program loop after the program pulse apply operation has been completed. ### Claim 3 (depends on 2) The memory device according to claim 2, wherein the control logic controls the peripheral circuit to resume the program verify operation of the suspended n-th program loop in response to the resume command. ### Claim 4 (depends on 1) The memory device according to claim 1, wherein when the suspend command is received during the program verify operation of the n-th program loop, the control logic controls the peripheral circuit to suspend the n-th program loop after an ongoing state verification operation, among respective state verification operations for one or more program states included in the program verify operation of the n-th program loop, has been completed. ### Claim 5 (depends on 4) The memory device according to claim 4, wherein the control logic controls the peripheral circuit to resume an uncompleted state verification operation, among the respective state verification operations for the one or more program states included in the program verify operation of the suspended n-th program loop in response to the resume command. ### Claim 6 (depends on 1) The memory device according to claim 1, wherein the control logic is further configured to control the peripheral circuit to perform a read operation on the plurality of memory cells after the n-th program loop has been suspended. ### Claim 7 (depends on 6) The memory device according to claim 6, wherein the control logic controls the peripheral circuit to perform the read operation in response to the suspend command. ### Claim 8 (depends on 6) The memory device according to claim 6, wherein the control logic controls the peripheral circuit to perform the read operation in response to a read command received after the suspend command. ### Claim 9 (depends on 1) The memory device according to claim 1, wherein the recovery pulse apply operation is an operation of applying at least one recovery pulse to a selected word line coupled to the selected memory cells. ### Claim 10 (depends on 9) The memory device according to claim 9, wherein a level of the recovery pulse is lower than a level of a program pulse applied to the selected word line during the program pulse apply operation. ### Claim 11 (depends on 9) The memory device according to claim 9, wherein a level of the recovery pulse is equal to or higher than a level of a pass voltage applied to an unselected word line during the program pulse apply operation of the n-th program loop. ### Claim 12 (depends on 9) The memory device according to claim 9, wherein a level of the recovery pulse is constant, or increases as a count of the n-th program loop increases. ### Claim 13 A method of operating a memory device including a plurality of memory cells, the method comprising: suspending an n-th program loop among a plurality of program loops on selected memory cells among the plurality of memory cells in response to a suspend command received during the n-th program loop, where n is a natural number of 1 or more; and resuming the suspended n-th program loop after a recovery pulse apply operation has been performed in response to a resume command, wherein each of the plurality of program loops includes a program pulse apply operation and a program verify operation, and wherein the recovery pulse apply operation is an operation of compensating for charges detrapped from a channel area of the selected memory cells. ### Claim 14 (depends on 13) The method according to claim 13, further comprising performing a read operation on the plurality of memory cells in response to the suspend command or a read command after the n-th program loop is suspended. ### Claim 15 (depends on 13) The method according to claim 13, wherein the suspending of the n-th program loop comprises: receiving the suspend command during the program pulse apply operation of the n-th program loop; and suspending the n-th program loop after the program pulse apply operation has been completed. ### Claim 16 (depends on 15) The method according to claim 15, wherein the resuming of the suspended n-th program loop comprises resuming the program verify operation of the suspended n-th program loop. ### Claim 17 (depends on 13) The method according to claim 13, wherein the suspending of the n-th program loop comprises: receiving the suspend command during the program verify operation of the n-th program loop; and suspending the n-th program loop after completion of an ongoing state verification operation, among respective state verification operations for one or more program states that are included in the program verify operation of the n-th program loop. ### Claim 18 (depends on 17) The method according to claim 17, wherein the resuming of the suspended n-th program loop comprises resuming an uncompleted state verification operation, among the respective state verification operations for the one or more program states included in the program verify operation of the suspended n-th program loop. ### Claim 19 (depends on 13) The method according to claim 13, wherein the recovery pulse apply operation applies at least one recovery pulse to a selected word line coupled to the selected memory cells. ### Claim 20 (depends on 19) The method according to claim 19, wherein a level of the recovery pulse is lower than a level of a program pulse applied to the selected word line and is equal to or higher than a level of a pass voltage applied to an unselected word line, during the program pulse apply operation. ### Claim 21 An operating method of a memory device, the operating method comprising: suspending, in response to a suspend command for a program operation on a storage unit, a start of a state verification operation on one among program states, the state verification operation being a part of the program operation; applying, in response to a resume command for the program operation, one or more recovery pulses to the storage unit; and resuming, upon completion of the applying, the program operation from the suspended start.