# US 2021/0280261 A1 · Non volatile flash memory with improved verification recovery and column seeding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280261 A1 - Document ID: US20210280261A1 - Status: Published application - Kind: A1 - Application number: 16/808,955 - Filed: 2020-03-04 - Published: 2021-09-09 - Earliest claimed: 2020-03-04 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Xiang YANG - Web page: https://patentgrep.com/patent/US20210280261A1 ## CPC - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells} - G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus is described. The apparatus includes a non volatile memory chip. The non volatile memory chip includes an interface to receive access commands, a three dimensional array of non volatile storage cells, and, a controller to orchestrate removal of charge in a column of stacked ones of the non volatile storage cells after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount. The removal of the charge pushes the charge out of the column by changing respective word line potentials along a particular direction along the column. Cells that are coupled to the column are programmed in the particular direction. Disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction. ## Claims ### Claim 1 An apparatus, comprising: a non-volatile memory chip, comprising: an interface to receive access commands; a three dimensional array of non-volatile storage cells; and, a controller to orchestrate removal of charge in a column of stacked ones of the non-volatile storage cells after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount, wherein the removal of the charge pushes the charge out of the column by changing respective word line potentials along a particular direction along the column, and wherein, cells that are coupled to the column are programmed in the particular direction, and wherein, disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction. ### Claim 2 (depends on 1) The apparatus of claim 1 wherein the cells are flash cells. ### Claim 3 (depends on 1) The apparatus of claim 1 wherein the particular direction is away from a bit line that is coupled to an end of the column. ### Claim 4 (depends on 3) The apparatus of claim 3 wherein the bit line is coupled to a top end of the column, wherein, the top end is father away from the non-volatile memory chip's substrate than a bottom end of the column. ### Claim 5 (depends on 1) The apparatus of claim 1 wherein the particular direction is toward a bottom end of the column, wherein, the bottom end is closer to the non-volatile memory chips' substrate than a top end of the column. ### Claim 6 (depends on 1) The apparatus of claim 1 wherein the controller is also to seed the column with second charge that is opposite in polarity to the charge in the direction opposite that of the particular direction. ### Claim 7 (depends on 6) The apparatus of claim 6 wherein the second charge is positive charge. ### Claim 8 (depends on 6) The apparatus of claim 6 wherein the second charge is to flow through an on transistor positioned at an end of the column that is also not a storage cell transistor. ### Claim 9 (depends on 1) The apparatus of claim 1 wherein the controller is at least partially implemented with logic circuitry. ### Claim 10 An apparatus, comprising: a non volatile memory chip, comprising: an interface to receive access commands; a three dimensional array of non volatile storage cells; and, a controller to orchestrate seeding a column of stacked ones of the non volatile storage cells with charge in preparation for a next program iteration after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount, wherein, cells that are coupled to the column are programmed in a particular direction along the column on a word line by word line basis, wherein, the particular direction points toward an end of the column where the seeding is injected, and wherein, disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction. ### Claim 11 (depends on 10) The apparatus of claim 10 wherein the cells are flash cells. ### Claim 12 (depends on 10) The apparatus of claim 10 wherein the direction is away from a bit line that is coupled to another opposite end of the column. ### Claim 13 (depends on 12) The apparatus of claim 12 wherein the bit line is coupled to a top end of the column. ### Claim 14 (depends on 10) The apparatus of claim 10 wherein the direction is toward a bottom end of the column. ### Claim 15 (depends on 10) The apparatus of claim 10 wherein the column is simultaneously seeded with charge from an opposite end of the column. ### Claim 16 A computing system, comprising: a plurality of processing cores; a peripheral control hub; a system memory controller; and, a non-volatile memory device coupled to one of the peripheral control hub and the system memory controller, the non-volatile memory device comprising a non-volatile memory chip, the non-volatile memory chip, comprising: an interface to receive access commands; a three dimensional array of non-volatile storage cells; and a controller to orchestrate removal of charge in a column of stacked ones of the non-volatile storage cells after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount, wherein the removal of the charge pushes the charge out of the column by changing respective word line potentials along a particular direction along the column, and wherein, cells that are coupled to the column are programmed in the particular direction, and wherein, disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction. ### Claim 17 (depends on 16) The computing system of claim 16 wherein the cells are flash cells. ### Claim 18 (depends on 16) The computing system of claim 16 wherein the particular direction is away from a bit line that is coupled to an end of the column. ### Claim 19 (depends on 18) The computing system of claim 18 wherein the bit line is coupled to a top end of the column, wherein, the top end is father away from the non-volatile memory chip's substrate than a bottom end of the column. ### Claim 20 (depends on 16) The computing system of claim 16 wherein the particular direction is toward a bottom end of the column, wherein, the bottom end is closer to the non-volatile memory chip's substrate than a top end of the column.