# US 2021/0280253 A1 · Sequential write and sequential write verify in memory device

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- Number: US 2021/0280253 A1
- Document ID: US20210280253A1
- Status: Published application
- Kind: A1
- Application number: 17/328,744
- Filed: 2021-05-24
- Published: 2021-09-09
- Earliest claimed: 2014-12-11
- Assignees: Micron Technolgy, Inc.
- Applicants: Micron Technolgy, Inc.
- Inventors: Koji Sakui
- Web page: https://patentgrep.com/patent/US20210280253A1

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/10: Programming or data input circuits
- G11C 16/30: Power supply circuits
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

## Claims

### Claim 1

An apparatus comprising:
a data line;
a first memory cell included in a first memory cell string;
a second memory cell included in a second memory cell string;
an access line shared by the first and second memory cells; and
a module to:
change a value of a threshold voltage of the first memory cell during a first time interval of an operation of the apparatus;
change a value of a threshold voltage of the second memory cell during a second time interval of the operation; and
determine, during a third time interval after the first and second time intervals, whether the first memory cell reaches a first target threshold voltage and whether the second memory cell reaches a second target voltage.