# US 2021/0280252 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280252 A1 - Document ID: US20210280252A1 - Status: Published application - Kind: A1 - Application number: 17/177,083 - Filed: 2021-02-16 - Published: 2021-09-09 - Earliest claimed: 2020-03-05 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Osamu KOBAYASHI - Web page: https://patentgrep.com/patent/US20210280252A1 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 5/144: {Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/30: Power supply circuits - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor device includes a level conversion circuit. The level conversion circuit includes a first transistor, a second transistor, a current limiting element, and a voltage adjusting circuit. The first transistor includes a gate connected to an input node. A signal corresponding to a first power supply voltage is input to the input node. The second transistor has a source connected to a drain of the first transistor, a drain connected to a second power supply voltage that is higher than the first power supply voltage, and a gate connected to a first node. The current limiting element is electrically connected between the first node and an output node. The voltage adjusting circuit adjusts a voltage of the first node in accordance with the signal input to the input node. ## Claims ### Claim 1 A semiconductor device comprising: a level conversion circuit, wherein the level conversion circuit includes: a first transistor having a gate connected to an input node to which a signal corresponding to a first power supply voltage is input; a second transistor having a drain connected to a second power supply voltage higher than the first power supply voltage, a source connected to a source of the first transistor, and a gate connected to a first node; a current limiting element electrically connected between the first node and an output node; and a voltage adjusting circuit configured to adjust a voltage of the first node in accordance with the signal input to the input node. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first transistor is an enhancement-type transistor, and the second transistor is a depletion-type transistor. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the current limiting element includes: a first resistance element having one end electrically connected to the first node and the other end electrically connected to the output node. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the current limiting element includes: a third transistor having a gate and a source that are electrically connected to the first node and a drain electrically connected to the output node. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the third transistor is a depletion-type transistor. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the voltage adjusting circuit includes: a fourth transistor maintained in an off state during a period in which the first transistor is on and maintained in an on state during a period in which the first transistor is off. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the level conversion circuit further includes a fifth transistor having a gate connected to the first power supply voltage, a drain connected to the output node, and a source connected to a second node, and the fourth transistor includes a gate connected to the input node, a source connected to a ground voltage, and a drain connected to the first node. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein the level conversion circuit further includes a fifth transistor having a gate connected to the first power supply voltage, a drain connected to the output node, and source connected to a second node, and the fourth transistor includes a gate connected to the input node, a source connected to a ground voltage, and a drain connected to the first node. ### Claim 9 (depends on 6) The semiconductor device according to claim 6, wherein the level conversion circuit further includes: a fifth transistor having a gate connected to the first power supply voltage, a drain connected to the output node, and a source connected to a second node; and a second resistance element having one end connected to the input node, and the fourth transistor includes a base connected to the other end of the second resistance element, an emitter connected to a ground voltage, and a collector connected to the first node. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the level conversion circuit further includes: a fourth transistor having a gate connected to the first power supply voltage, a source connected to a second node, and a drain connected to the first node; and a fifth transistor having a gate connected to the first power supply potential, a drain connected to the output node, and a source connected to the second node. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, further comprising: a memory cell array, wherein the level conversion circuit is disposed around the memory cell array. ### Claim 12 A semiconductor device comprising: a memory cell array having a plurality of blocks; and a row decoder circuit including a block decoder configured to generate a block selection signal using which one of the blocks is selected, wherein the block decoder includes a level conversion circuit that outputs the block selection signal, the level conversion circuit including: a first transistor having a gate connected to an input node to which a signal corresponding to a first power supply voltage is input; a second transistor having a drain connected to a second power supply voltage higher than the first power supply voltage, a source connected to a source of the first transistor, and a gate connected to a first node; a current limiting element electrically connected between the first node and an output node through which the block selection signal is output; and a voltage adjusting circuit configured to adjust a voltage of the first node in accordance with the signal input to the input node. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the first transistor is an enhancement-type transistor, and the second transistor is a depletion-type transistor. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, wherein the current limiting element includes a first resistance element having one end electrically connected to the first node and the other end electrically connected to the output node. ### Claim 15 (depends on 12) The semiconductor device according to claim 12, wherein the current limiting element includes a third transistor having a gate and a source that are electrically connected to the first node and a drain electrically connected to the output node. ### Claim 16 (depends on 12) The semiconductor device according to claim 12, wherein the voltage adjusting circuit includes a fourth transistor maintained in an off state during a period in which the first transistor is on and maintained in an on state during a period in which the first transistor is off. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein the level conversion circuit further includes a fifth transistor having a gate connected to the first power supply voltage, a drain connected to the output node, and a source connected to a second node, and the fourth transistor includes a gate connected to the input node, a source connected to a ground voltage, and a drain connected to the first node. ### Claim 18 (depends on 16) The semiconductor device according to claim 16, wherein the level conversion circuit further includes a fifth transistor having a gate connected to the first power supply voltage, a drain connected to the output node, and source connected to a second node, and the fourth transistor includes a gate connected to the input node, a source connected to a ground voltage, and a drain connected to the first node. ### Claim 19 (depends on 16) The semiconductor device according to claim 16, wherein the level conversion circuit further includes: a fifth transistor having a gate connected to the first power supply voltage, a drain connected to the output node, and a source connected to a second node; and a second resistance element having one end connected to the input node, and the fourth transistor includes a base connected to the other end of the second resistance element, an emitter connected to a ground voltage, and a collector connected to the first node. ### Claim 20 (depends on 12) The semiconductor device according to claim 12, wherein the level conversion circuit further includes: a fourth transistor having a gate connected to the first power supply voltage, a source connected to a second node, and a drain connected to the first node; and a fifth transistor having a gate connected to the first power supply potential, a drain connected to the output node, and a source connected to the second node.