# US 2021/0280247 A1 · Soft reset for multi-level programming of memory cells in non-von neumann architectures

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- Number: US 2021/0280247 A1
- Document ID: US20210280247A1
- Status: Published application
- Kind: A1
- Application number: 17/329,008
- Filed: 2021-05-24
- Published: 2021-09-09
- Earliest claimed: 2020-02-18
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Deepak Kamalanathan; Siddarth Krishnan; Archana Kumar; Fuxi Cai; Federico Nardi
- Web page: https://patentgrep.com/patent/US20210280247A1

## CPC

- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- G11C 11/5614: {using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/0038: {Power supply circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/0078: {Write using current through the cell}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

## Claims

### Claim 1

A memory cell comprising:
a memory element;
a transistor in series with the memory element; and
a voltage control circuit, wherein the voltage control circuit is configured to:
apply one or more first voltage pulses to the transistor to cause the memory element to transition from a low-current state to a high-current state;
apply one or more second voltage pulses to the transistor to cause the memory element to transition from the high-current state to a state between the high-current state and the low-current state;
determine whether the state corresponds to a predetermined state; and
apply one or more additional voltage pulses to the transistor until the state corresponds to the predetermined state.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein determining whether the state corresponds to the predetermined state comprises:
measuring a current through the memory element; and
comparing the current through the memory element to a predetermined current corresponding to the predetermined state.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the one or more additional voltage pulses applied to the memory element comprise approximately equal voltage pulses.

### Claim 4 (depends on 1)

The memory cell of claim 1, wherein the one or more additional voltage pulses applied to the memory element comprise voltage pulses of increasing magnitude.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein the one or more first voltage pulses are applied across a drain and a source of the transistor.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein the one or more first voltage pulses are applied to a gate of the transistor.

### Claim 7 (depends on 6)

The memory cell of claim 6, wherein the one or more first voltage pulses correspond to a predetermined starting point for a current level at or above a current level for the state.

### Claim 8

A memory cell comprising:
a memory element; and
a transistor, wherein:
a first voltage applied to the transistor causes the memory element to transition from a low-current state to a high-current state; and
a second voltage applied to the transistor causes the memory element to transition from the high-current state to a state between the high-current state and the low-current state.

### Claim 9 (depends on 8)

The memory cell of claim 8, wherein:
the second voltage comprises a plurality of voltage pulses.

### Claim 10 (depends on 8)

The memory cell of claim 8, wherein:
the low-current state corresponds to a logic 0; and
the high-current state corresponds to a logic 1.

### Claim 11 (depends on 8)

The memory cell of claim 8, wherein the memory element comprises a filamentary Random Access Memory (RAM).

### Claim 12 (depends on 11)

The memory cell of claim 11, wherein the filamentary RAM comprises a resistive RAM (ReRAM).

### Claim 13 (depends on 8)

The memory cell of claim 8, wherein the memory element is part of a non-Von Neumann architecture.

### Claim 14 (depends on 8)

The memory cell of claim 8, wherein the state corresponds to a current level of less than 1 μA through the memory element.

### Claim 15 (depends on 14)

The memory cell of claim 14, wherein the high-current state corresponds to a current level of approximately 100 μA through the memory element.

### Claim 16 (depends on 8)

The memory cell of claim 8, wherein the state is one of a plurality of intermediate states between the high-current state and the low-current state.

### Claim 17 (depends on 16)

The memory cell of claim 16, wherein the plurality of intermediate states comprises at least three intermediate states, each having a non-overlapping current range between 10 nA and 1 μA.

### Claim 18 (depends on 16)

The memory cell of claim 16, wherein each of the plurality of intermediate states corresponds to a different tunneling barrier length in the memory element.

### Claim 19 (depends on 18)

The memory cell of claim 18, wherein a width of a filament in the memory element is approximately the same for each of the plurality of intermediate states.