# US 2021/0280245 A1 · Resistive random access memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0280245 A1
- Document ID: US20210280245A1
- Status: Published application
- Kind: A1
- Application number: 17/330,248
- Filed: 2021-05-25
- Published: 2021-09-09
- Earliest claimed: 2017-11-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Der CHIH; Chung-Cheng CHOU; Wen-Ting CHU
- Web page: https://patentgrep.com/patent/US20210280245A1

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/253: {having three or more electrodes, e.g. transistor-like devices}
- H10N 70/841: {Electrodes}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2213/79: Array wherein the access device being a transistor
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

## Claims

### Claim 1

A memory device, comprising:
a first cell array comprising a first plurality of bit cells using a first variable resistance dielectric layer to transition between logic states;
a second cell array comprising a second plurality of bit cells using a second variable resistance dielectric layer to transition between logic states;
a third cell array comprising a third plurality of bit cells using a third variable resistance dielectric layer to transition between logic states; and
a control logic circuit configured to cause a first information bit to be written into respective bit cells of the first and second cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, and cause a second information bit to be written into a single bit cell of the third cell array as an original logic state of the second information bit,
wherein
the first variable resistance dielectric layer has a first diameter, and
the third variable resistance dielectric layer has a second diameter that is different from the first diameter.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the first, second, and third variable resistance dielectric layers are formed based on a same recipe of deposition equipment, and share substantially an identical thickness and/or crystalline structure.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the first diameter is smaller than the second diameter.

### Claim 4 (depends on 1)

The memory device of claim 1, further comprising:
a sensing circuit, coupled to the first, second and third pluralities of bit cells, and configured to determine the first information bit's original logic state present by the respective bit cells of the first and second cell arrays by comparing respective current signals conducting through the respective bit cells of the first and second cell arrays.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein:
the first and second cell arrays are disposed at respective opposite sides of the sensing circuit; and
the sensing circuit is further configured to determine the second information bit's original logic state present by the single bit cell of the third cell array by comparing a current signal conducting through the single bit cell of the third cell array with a reference current signal.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein:
each of the first, second and third pluralities of bit cells comprises a resistive random access memory (RRAM) bit cell; and
the first, second and third cell arrays are formed as a memory macro disposed on a single chip.

### Claim 7

A memory device, comprising:
a first cell array comprising a first plurality of bit cells;
a second cell array comprising a second plurality of bit cells;
a third cell array comprising a third plurality of bit cells; and
a control logic circuit configured to cause a first information bit to be written into respective bit cells of the first and second cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, and a second information bit into a bit cell of the third cell array as an original logic state of the second information bit, such that the respective bit cells of the first and second cell arrays have a first endurance and the bit cell of the third cell array has a second endurance.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein:
the first endurance comprises a maximum number of cycles for which the respective bit cells of the first and second cell arrays can transition between respective different resistance states; and
the second endurance comprises a maximum number of cycles for which the bit cell of the third cell array can transition between respective different resistance states.

### Claim 9 (depends on 7)

The memory device of claim 7, wherein the first endurance is substantially higher than the second endurance.

### Claim 10 (depends on 7)

The memory device of claim 7, wherein:
the first, second, and third pluralities of bit cells have a substantially identical variable resistance dielectric layer; and
the variable resistance dielectric layer comprises a thickness and crystalline structure that is formed by using a same recipe of deposition equipment.

### Claim 11 (depends on 7)

The memory device of claim 7, further comprising:
a sensing circuit, coupled to the first, second, and third cell arrays, and configured to read out the original logic state of the first information bit present by the respective bit cells of the first and second cell arrays by comparing respective current signals conducting through the respective bit cells of the first and second cell arrays.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the first and second cell arrays are disposed at respective opposite sides of the sensing circuit.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the sensing circuit is further configured to read out the original logic state of the second information bit present by the bit cell of the third cell array by comparing a current signal conducting through the bit cell of the third cell array with a reference current signal.

### Claim 14 (depends on 7)

The memory device of claim 7, wherein each of the first, second, and third pluralities of bit cells comprises a resistive random access memory (RRAM) bit cell.

### Claim 15 (depends on 7)

The memory device of claim 7, wherein:
the first, second, and third cell arrays are formed as a memory macro disposed on a single chip; and
the first, second, and third pluralities of bit cells have respective variable resistance dielectric layers that are formed by a same recipe of deposition equipment but have different diameters.

### Claim 16

A memory device, comprising:
a first cell array comprising a first plurality of bit cells using a first variable resistance dielectric layer to transition between logic states;
a second cell array comprising a second plurality of bit cells using a second variable resistance dielectric layer to transition between logic states;
a third cell array comprising a third plurality of bit cells using a third variable resistance dielectric layer to transition between logic states; and
a control logic circuit configured to cause a first information bit to be written into respective bit cells of the first and second cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, and cause a second information bit to be written into a single bit cell of the third cell array as an original logic state of the second information bit,
wherein the first, second, and third variable resistance dielectric layers are formed based on a same recipe of deposition equipment, and have at least two different diameters.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein:
each of the first and second variable resistance dielectric layers has a first diameter;
the third variable resistance dielectric layer has a second diameter; and
the first diameter is smaller than the second diameter.

### Claim 18 (depends on 16)

The memory device of claim 16, further comprising:
a sensing circuit, coupled to the first, second and third pluralities of bit cells, and configured to determine the first information bit's original logic state present by the respective bit cells of the first and second cell arrays by comparing respective current signals conducting through the respective bit cells of the first and second cell arrays.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein:
the first and second cell arrays are disposed at respective opposite sides of the sensing circuit; and
the sensing circuit is further configured to determine the second information bit's original logic state present by the single bit cell of the third cell array by comparing a current signal conducting through the single bit cell of the third cell array with a reference current signal.

### Claim 20 (depends on 16)

The memory device of claim 16, wherein:
each of the first, second and third pluralities of bit cells comprises a resistive random access memory (RRAM) bit cell; and
the first, second and third cell arrays are formed as a memory macro disposed on a single chip.