# US 2021/0280241 A1 · Semiconductor memory device and method for operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280241 A1 - Document ID: US20210280241A1 - Status: Published application - Kind: A1 - Application number: 16/984,743 - Filed: 2020-08-04 - Published: 2021-09-09 - Earliest claimed: 2020-03-03 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Hyung Jin CHOI - Web page: https://patentgrep.com/patent/US20210280241A1 ## CPC - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C 2211/5621: Multilevel programming verification - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract There are provided a semiconductor memory device and a method for operating the same. The semiconductor memory device includes: a memory cell array with a plurality of memory cells programmed to a plurality of program states; a peripheral circuit configured for performing a program operation on selected memory cells among the plurality of memory cells through a plurality of program loops; a current sensing circuit for determining a verify result of each of the plurality of program states by performing an individual state current sensing operation on the selected memory cells among the memory cells; and a control logic for controlling the current sensing circuit to perform the individual state current sensing operation, based on a number of program loops, among a plurality of program loops, that are performed. ## Claims ### Claim 1 A semiconductor memory device comprising: a memory cell array with a plurality of memory cells programmed to a plurality of program states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells through a plurality of program loops; a current sensing circuit configured to determine a verify result of each of the plurality of program states by performing an individual state current sensing operation on the selected memory cells among the memory cells; and a control logic configured to control the current sensing circuit to perform the individual state current sensing operation, based on a number of program loops, among a plurality of program loops, that are performed. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the control logic: controls the plurality of program loops to be sequentially performed by controlling the peripheral circuit, and controls the current sensing circuit to skip the individual state current sensing operation while an initial m program loops among the plurality of program loops are being performed, wherein m is a positive integer greater than 1. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the control logic: controls the plurality of program loops that correspond to the plurality of program states to be sequentially performed, controls the peripheral circuit to perform program loops that correspond to a first program state among the plurality of program loops in a program operation on the first program state among the plurality of program states, and controls the current sensing circuit to skip the individual state current sensing operation that corresponds to the first program state during the initial m program loops among the program loops that correspond to the first program state. ### Claim 4 (depends on 3) The semiconductor memory device of claim 3, wherein the control logic controls the current sensing circuit to perform the individual state current sensing operation that corresponds to the first program state from an (m+1)th program loop among the program loops that correspond to the first program state. ### Claim 5 (depends on 3) The semiconductor memory device of claim 3, wherein the control logic: controls the peripheral circuit to sequentially perform program operations on second to nth program states among the plurality of program states, controls peripheral circuit to sequentially perform program loops that correspond to any one program state among the second to nth program states among the plurality of program loops, in a program operation that corresponds to the one program state, and controls the current sensing circuit to skip the individual state current sensing operation that corresponds to the one program state during an initial k program loops among the program loops that correspond to the one program state, wherein k is a positive integer greater than 1. ### Claim 6 (depends on 5) The semiconductor memory device of claim 5, wherein the control logic controls the current sensing circuit to perform the individual state current sensing operation that corresponds to the one program state from a (k+1)th program loop among the program loops that correspond to the one program state. ### Claim 7 (depends on 1) The semiconductor memory device of claim 1, wherein the peripheral circuit includes a plurality of page buffers connected to bit lines of the memory cell array, and wherein the plurality of page buffers supplies a sensing current to the bit lines to sense a threshold voltage of the selected memory cells in a verify operation, senses a current amount of the bit lines and then latches the sensed current amount as sensing data, and generates a sensing voltage by using the latched sensing data. ### Claim 8 (depends on 7) The semiconductor memory device of claim 7, wherein the current sensing circuit generates a reference voltage based on an allow bit that is received from the control logic in the individual state current sensing operation, and generates a pass signal or a fail signal by comparing the reference voltage with the sensing voltage. ### Claim 9 (depends on 8) The semiconductor memory device of claim 8, wherein the control logic determines whether the verify operation that corresponds to each of the plurality of program states has been completed, based on the pass signal or the fail signal. ### Claim 10 (depends on 1) The semiconductor memory device of claim 1, wherein the control logic includes: a program pulse counter configured to generate program pulse count values that correspond to each of the plurality of program states by counting a number of times a program pulse is applied to the selected word line in a program operation that corresponds to each of the plurality of program states, and a sensing mode controller configured to generate a current sensing control signal for determining a sensing mode of the current sensing circuit, based on the program pulse count values. ### Claim 11 (depends on 10) The semiconductor memory device of claim 10, wherein the current sensing circuit performs the individual state current sensing operation or skips the individual state current sensing operation, based on the current sensing control signal. ### Claim 12 A semiconductor memory device comprising: a memory cell array with a plurality of memory cells programmed to first to nth program states, wherein n is a positive integer greater than 2; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells through a plurality of program loops; a current sensing circuit configured to perform individual state current sensing operations, respectively corresponding to the first to nth program states on the selected memory cells among the memory cells; and a control logic configured to control the peripheral circuit to perform the program operation, and control the current sensing circuit to skip the individual state current sensing operation that corresponds to the first program state during an initial m program loops among the plurality of program loops, wherein m is a positive integer greater than 1. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, wherein the control logic: controls the peripheral circuit to sequentially perform the plurality of program loops that correspond to the first to nth program states in the program operation, controls the peripheral circuit to sequentially perform program loops that correspond to any one program state among the second to nth program states among the plurality of program loops, in a program operation that corresponds to the one program state during the program operation, and controls the current sensing circuit to skip the individual state current sensing operation that corresponds to the one program state during an initial k program loops among the program loops that correspond to the one program state, wherein k is a positive integer greater than 1. ### Claim 14 (depends on 12) The semiconductor memory device of claim 12, wherein the peripheral circuit includes a plurality of page buffers that are connected to bit lines of the memory cell array, wherein the plurality of page buffers supplies a sensing current to the bit lines to sense a threshold voltage of the selected memory cells in a verify operation during the program operation, senses a current amount of the bit lines and then latches the sensed current amount as sensing data, and generates a sensing voltage by using the latched sensing data. ### Claim 15 (depends on 14) The semiconductor memory device of claim 14, wherein the current sensing circuit generates a reference voltage based on an allow bit that is received from the control logic in the individual state current sensing operation, and generates a pass signal or a fail signal by comparing the reference voltage with the sensing voltage. ### Claim 16 (depends on 15) The semiconductor memory device of claim 15, wherein the control logic determines whether the verify operation that corresponds to each of the first to nth program states has been completed, based on the pass signal or the fail signal. ### Claim 17 (depends on 12) The semiconductor memory device of claim 12, wherein the control logic includes: a program pulse counter configured to generate program pulse count values that correspond to each of the plurality of program states by counting a number of times a program pulse is applied to the selected word line in a program operation that corresponds to each of the first to nth program states, and a sensing mode controller configured to generate a current sensing control signal to determine a sensing mode of the current sensing circuit, based on the program pulse count values. ### Claim 18 (depends on 17) The semiconductor memory device of claim 17, wherein the current sensing circuit performs the individual state current sensing operation or skips the individual state current sensing operation, based on the current sensing control signal. ### Claim 19 A method for operating a semiconductor memory device, the method comprising: performing a first program operation that corresponds to a first program state among a plurality of program states; and performing a second program operation that corresponds to a second program state of threshold voltage distribution is higher than that of the first program state, after the first program operation is completed, wherein a plurality of first program loops are sequentially performed in the first program operation, wherein each of initial m (m is a positive integer greater than 1) program loops among the plurality of first program loops includes a program pulse application operation and a verify operation, and wherein each of (m+1)th to last program loops among the plurality of first program loops includes the program pulse application operation, the verify operation, and an individual state current sensing operation that corresponds to the first program state. ### Claim 20 (depends on 19) The method of claim 19, wherein the individual state current sensing operation that corresponds to the first program state is skipped in each of the initial m program loops. ### Claim 21 (depends on 19) The method of claim 19, wherein a plurality of second program loops are sequentially performed in the second program operation, wherein each of an initial k (k is a positive integer greater than 1) program loops among the plurality of second program loops includes the program pulse application operation and the verify operation, and wherein each of (k+1)th to last program loops among the plurality of second program loops includes the program pulse application operation, the verify operation, and an individual state current sensing operation that corresponds to the second program state.