# US 2021/0280239 A1 · Analog neural memory array in artificial neural network with substantially constant array source impedance with adaptive weight mapping and distributed power

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- Number: US 2021/0280239 A1
- Document ID: US20210280239A1
- Status: Published application
- Kind: A1
- Application number: 16/986,812
- Filed: 2020-08-06
- Published: 2021-09-09
- Earliest claimed: 2020-03-05
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.
- Inventors: Hieu Van Tran; Thuan VU; Stephen TRINH; Stanley HONG; Anh LY; Vipin Tiwari
- Web page: https://patentgrep.com/patent/US20210280239A1

## CPC

- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/063: using electronic means
- G06N 3/065: Analogue means
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/0425: {comprising cells containing a merged floating gate and select transistor}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- H03F 3/005: {using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence)}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03M 1/007: {among different resolutions}
- H03M 1/145: {the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence)}
- H03M 1/164: {the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence)}
- H03M 1/466: {using switched capacitors}
- G06N 3/048: Activation functions
- H03F 2203/45526: the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
- H03F 2203/45536: the FBC comprising a switch and being coupled between the LC and the IC
- H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14)
- H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array}
- H03M 1/56: Input signal compared with linear ramp
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H03F: AMPLIFIERS
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

## Claims

### Claim 1

An analog neural memory system comprising:
an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a different bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a different dummy bit line in a plurality of dummy bitlines;
a set of dummy bit line switches arranged on a first end of the array, each of the set of dummy bit line switches coupled to one of the dummy bit lines in the plurality of dummy bitlines; and
a set of bit line switches arranged on a second end of the array opposite the first end of the array, each of the set of bit line switches coupled to one of the bit lines in the plurality of bit lines.

### Claim 2 (depends on 1)

The system of claim 1, wherein each of the set of bit line switches is configured to pull the coupled dummy bit line to ground.

### Claim 3 (depends on 2)

The system of claim 2, wherein array bit line interconnect impedance remains substantially constant when cells attached to the plurality of bit lines are selected for a read operation.

### Claim 4 (depends on 1)

The system of claim 1, wherein two or more of the bit line transistors in the first set of bit line transistors are connected to a common ground.

### Claim 5 (depends on 1)

The system of claim 1, wherein two or more of the bit lines are coupled to one another.

### Claim 6 (depends on 1)

The system of claim 1, wherein array bit line interconnect impedance remains substantially constant when cells attached to the plurality of bit lines are selected for a read operation.

### Claim 7 (depends on 1)

The system of claim 1, wherein the second set of bit line transistors couples to one or more of a sensing circuit, a summer, or an analog-to-digital converter circuit.

### Claim 8 (depends on 1)

The system of claim 1, wherein the non-volatile memory cells in the array are split gate flash memory cells.

### Claim 9 (depends on 1)

The system of claim 1, wherein the non-volatile memory cells in the array are stacked gate flash memory cells.

### Claim 10 (depends on 1)

The system of claim 1, further comprising a summer for summing outputs from one or more bit lines.

### Claim 11 (depends on 10)

The system of claim 10, wherein the summer is adjustable based on a variable resistor.

### Claim 12 (depends on 10)

The system of claim 10, wherein the summer is adjustable based on a variable capacitor.

### Claim 13 (depends on 10)

The system of claim 10, further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.

### Claim 14 (depends on 13)

The system of claim 13, wherein the analog-to-digital converter comprises a successive approximation register.

### Claim 15 (depends on 14)

The system of claim 14, wherein the analog-to-digital converter is a pipelined analog-to-digital converter.

### Claim 16 (depends on 1)

The system of claim 1, further comprising:
a source line coupled to a source line terminal of a row of non-volatile memory cells; and
a source line transistor configured to pull the source line to ground.

### Claim 17 (depends on 16)

The system of claim 16, wherein array interconnect impedance remains substantially constant when cells attached to the bit lines are selected for operation.

### Claim 18 (depends on 16)

The system of claim 16, wherein the second set of bit line transistors couples to one or more of a sensing circuit, a summer, or an analog-to-digital converter circuit

### Claim 19 (depends on 16)

The system of claim 16, wherein two or more of the bit line transistors in the first set of bit line transistors are connected to a common ground.

### Claim 20

An analog neural memory system comprising:
a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a different bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a different dummy bit line in a plurality of dummy bitlines;
a second array of non-volatile memory cells, the cells in the second array arranged in rows and columns, wherein a second plurality of columns of cells in the second array is connected to a different bit line in the plurality of bit lines and a second plurality of columns of cells in the second array is connected to a different dummy bit line in a plurality of dummy bitlines; and
a set of multiplexors coupled to the first array and the second array and coupled to ground;
wherein array interconnect impedance of the first array and the second array remain substantially constant when cells attached to the bit lines are selected for operation.

### Claim 21 (depends on 20)

The system of claim 20, wherein the non-volatile memory cells in the first array and the second array are split gate flash memory cells.

### Claim 22 (depends on 20)

The system of claim 20, wherein the non-volatile memory cells in the first array and the second array are stacked gate flash memory cells.

### Claim 23 (depends on 20)

The system of claim 20, further comprising a summer for summing outputs from one or more bit lines.

### Claim 24 (depends on 23)

The system of claim 23, wherein the summer is adjustable based on a variable resistor.

### Claim 25 (depends on 23)

The system of claim 23, wherein the summer is adjustable based on a variable capacitor.

### Claim 26 (depends on 23)

The system of claim 23, further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.

### Claim 27 (depends on 26)

The system of claim 26, wherein the analog-to-digital converter comprises a successive approximation register.

### Claim 28 (depends on 27)

The system of claim 27, wherein the analog-to-digital converter is a pipelined analog-to-digital converter.

### Claim 29

A method of operating an analog neural memory system comprising a first array comprising non-volatile memory cells arranged in rows and columns, a second array comprising non-volatile memory cells arranged in rows and columns, column multiplexors, local bit lines, and global bit lines, the method comprising:
selecting, by the column multiplexors, a local bit line of the first array or a local bit line of the second array, and coupling the selected bit line to a global bit line; and
multiplexing the global bit line with a second global bit line adjacent to the global bit line.

### Claim 30 (depends on 29)

The method of claim 29, further comprising:
summing outputs from one or more global bit lines.

### Claim 31

A method of operating an analog neural memory system comprising an array of non-volatile memory cells, the method comprising:
receiving, by a first n-bit analog-to-digital converter, a first output from the array;
receiving, by a second n-bit analog-to-digital converter, a second output from the array;
combining the first n-bit analog-to-digital converter with the second n-bit analog-to-digital converter to form a third analog-to-digital converter that generates a third output based on the first output and the second output, wherein the third output has a precision greater than n bits.

### Claim 32 (depends on 31)

The method of claim 31, wherein the first analog-to-digital converter is a serial analog-to-digital converter and the second analog-to-digital converter is a serial analog-to-digital converter.

### Claim 33 (depends on 31)

The method of claim 31, wherein the first analog-to-digital converter is a successive approximation converter and the second analog-to-digital converter is a successive approximation converter.

### Claim 34

An analog neural memory system comprising:
an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a dummy bit line in a plurality of dummy bitlines.

### Claim 35 (depends on 34)

The system of claim 34, wherein dummy bitlines are not used.

### Claim 36 (depends on 35)

The system of claim 35, wherein dummy bitlines are isolation bitlines.

### Claim 37 (depends on 35)

The system of claim 35, wherein memory cells of the dummy bitlines are partially or deeply programmed or partially erased.

### Claim 38

An analog neural memory system comprising:
an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a bit line in a plurality of bitlines, and weights of a neural network are distributed among the bitlines to maintain voltage drop or power consumption at a substantially equal level among the bitlines.

### Claim 39 (depends on 38)

The system of claim 38, wherein the non-volatile memory cells in the array are split gate flash memory cells.

### Claim 40 (depends on 38)

The system of claim 38, wherein the non-volatile memory cells in the array are stacked gate flash memory cells.

### Claim 41 (depends on 38)

The system of claim 38, further comprising a summer for summing outputs from one or more bit lines.

### Claim 42 (depends on 41)

The system of claim 41, wherein the summer is adjustable based on a variable resistor.

### Claim 43 (depends on 41)

The system of claim 41, wherein the summer is adjustable based on a variable capacitor.

### Claim 44 (depends on 41)

The system of claim 41, further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.

### Claim 45 (depends on 44)

The system of claim 44, wherein the analog-to-digital converter comprises a successive approximation register.

### Claim 46 (depends on 45)

The system of claim 45, wherein the analog-to-digital converter is a pipelined analog-to-digital converter.