# US 2021/0280237 A1 · Double-Pitch-Layout Techniques And Apparatus Thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280237 A1 - Document ID: US20210280237A1 - Status: Published application - Kind: A1 - Application number: 16/813,723 - Filed: 2020-03-09 - Published: 2021-09-09 - Earliest claimed: 2020-03-09 - Assignees: Mediatek Inc. - Applicants: MediaTek Inc. - Inventors: Tun-Fei Chien; Chia-Wei Wang - Web page: https://patentgrep.com/patent/US20210280237A1 ## CPC - G11C 11/417: for memory cells of the field-effect type - G11C 11/418: Address circuits - G11C 11/419: Read-write [R-W] circuits - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 7/18: Bit line organisation; Bit line lay-out - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array. ## Claims ### Claim 1 An apparatus, comprising: a substrate; and a memory circuit on the substrate, the memory circuit comprising an array of memory cells, control circuits, a word-line driver, and a plurality of input/output (I/O) circuits, the plurality of I/O circuits comprising a plurality of I/O pins comprising at least a first group of I/O pins and a second group of I/O pins, wherein: an M×N array of one-bit memory cells of the array of memory cells are grouped into N/2 two-column pairs of M×1 one-bit memory cells with respective I/O circuits of the plurality of I/O circuits, with M being a positive integer representative of a number of rows and N being a positive integer representative of a number of columns, each of the two-column pairs of M×1 memory cells comprises a first column of M×1 one-bit memory cells and a second column of M×1 one-bit memory cells, a layout of the first column of M×1 one-bit memory cells and a layout of the second column of M×1 one-bit memory cells are mirrored in horizontal and vertical axes such that the first group of I/O pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of the layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array wherein the memory circuit further comprises an internal power mesh, and wherein a pitch of the internal power mesh is different from a pitch of corresponding I/O pins of each of the one-bit memory cells. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein, wherein the plurality of I/O circuits comprise I/O pins comprising data-in (DI) pins, data-out (DO) pins, and BYTE pins, and wherein pitches of the I/O pins are equal to twice of a pitch of each of the one-bit memory cells. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the plurality I/O circuits of the two-column memory cell are located on the first side and the second side of the layout. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the plurality of I/O circuits comprise a pre-charging circuitry and a sense amplifier (SA). ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the memory circuit further comprises one additional control circuit that functions as a global signal buffer. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the memory circuit further comprises power switches located on the first side of the layout and the second side of the layout, and wherein the power switches control a power bias of the memory circuit. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein a pitch of the internal power mesh is four times a pitch of corresponding I/O pins of each of the one-bit memory cells. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein layouts of the M×N array of one-bit memory cells and the plurality of I/O circuits are grouped into N/4 of four-column groups of M×1 memory cells, wherein: each of the two-column pairs of M×1 memory cells comprises a first column of M×1 one-bit memory cells, a second column of M×1 one-bit memory cells, a third column of M×1 one-bit memory cells, and a fourth column of M×1 one-bit memory cells, layouts of the first column, second column, third column and fourth column of M×1 one-bit memory cells are mirrored in horizontal and vertical axes such that a first set of I/O pins corresponding to the first column of M×1 one-bit memory cells and a third set of I/O pins corresponding to the third column of M×1 one-bit memory cells are on the first side of the layout of the array, and a second set of I/O pins corresponding to the second column of M×1 one-bit memory cells and a fourth set of I/O pins corresponding to the fourth column of M×1 one-bit memory cells are on the second side of the layout of the array. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein layouts of the M×N array of one-bit memory cells and the I/O circuits are grouped into N/P of P columns of M×1 one-bit memory cells, with P being a positive integer, wherein: layouts of the P columns of M×1 one-bit memory cells are mirrored in horizontal and vertical axes such that the first group of I/O pins are on the first side of the layout of the array and the second group of I/O pins are on the second side of the layout of the array. ### Claim 10 An apparatus, comprising: a memory circuit comprising an array of memory cells, the array of memory cells comprising an M×N array of one-bit memory cells, with M being a positive integer representative of a number of rows and N being a positive integer representative of a number of columns, wherein: the M×N array of one-bit memory cells are grouped into N/2 two-column pairs of M×1 one-bit memory cells, and each of the two-column pairs of M×1 memory cells comprises a first column of M×1 one-bit memory cells and a second column of M×1 one-bit memory cells such that a layout of the first column of M×1 one-bit memory cells and a layout of the second column of M×1 one-bit memory cells are mirrored in horizontal and vertical axes wherein the memory circuit further comprises an internal power mesh, and wherein a pitch of the internal power mesh is different from a pitch of corresponding I/O pins of each of the one-bit memory cells. ### Claim 11 (depends on 10) The apparatus of claim 10, further comprising: a first group of input/output (I/O) pins; and a second group of I/O pins, wherein, for each of the two-column pairs of M×1 memory cells, the first group of I/O pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of the layout of the array of memory cells and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side of the layout of the array opposite the first side thereof.