# US 2021/0280236 A1 · Methods for row hammer mitigation and memory devices and systems employing the same

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- Number: US 2021/0280236 A1
- Document ID: US20210280236A1
- Status: Published application
- Kind: A1
- Application number: 17/328,419
- Filed: 2021-05-24
- Published: 2021-09-09
- Earliest claimed: 2018-08-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Dean D. Gans
- Web page: https://patentgrep.com/patent/US20210280236A1

## CPC

- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G11C 11/40603: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations}
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 11/408: Address circuits
- G11C 2211/4061: Calibration or ate or cycle tuning
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.

## Claims

### Claim 1

A method of operating a memory device, comprising:
determining a number of operations corresponding to a memory location during a refresh period; and
scheduling an extra non-periodic refresh operation for the memory location after the refresh period when the determined number of operations exceeds a predetermined threshold.

### Claim 2 (depends on 1)

The method of claim 1, wherein the extra non-periodic refresh operation is scheduled at the completion of the refresh period if a periodic refresh operation is not already scheduled at the completion of the refresh period.

### Claim 3 (depends on 1)

The method of claim 1, wherein the extra non-periodic refresh operation is scheduled at the completion of a second refresh period immediately following the refresh period if a periodic refresh operation is already scheduled at the completion of the refresh period.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
maintaining a count of refresh operations scheduled for the memory location.

### Claim 5 (depends on 4)

The method of claim 4, wherein maintaining the count comprises determining repeated refresh commands to the same memory location without a corresponding increase in a refresh address counter.

### Claim 6 (depends on 1)

The method of claim 1, wherein the operations comprise activations.

### Claim 7 (depends on 1)

The method of claim 1, wherein the refresh period comprises a base refresh interval.

### Claim 8 (depends on 7)

The method of claim 7, wherein the memory device is configured to be refreshed less often than every base refresh internal.

### Claim 9 (depends on 1)

The method of claim 1, wherein the scheduling the extra non-periodic refresh operation is dependent upon a refresh rate multiplier of the memory device being below a predetermined threshold value.

### Claim 10

A memory device, comprising:
a memory including a memory location; and
circuitry configured to:
determine a number of operations corresponding to the memory location during a refresh period; and
schedule an extra non-periodic refresh operation for the memory location after the refresh period when the determined number of operations exceeds a predetermined threshold.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the circuitry is configured to schedule the extra non-periodic refresh operation at the completion of the refresh period if a periodic refresh operation is not already scheduled at the completion of the refresh period.

### Claim 12 (depends on 10)

The memory device of claim 10, wherein the circuitry is configured to schedule the extra non-periodic refresh operation at the completion of a second refresh period immediately following the refresh period if a periodic refresh operation is already scheduled at the completion of the refresh period.

### Claim 13 (depends on 10)

The memory device of claim 10, wherein the circuitry is further configured to maintain a count of refresh operations scheduled for the memory location.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the circuitry is configured to maintain the count by determining repeated refresh commands to the same memory location without a corresponding increase in a refresh address counter.

### Claim 15 (depends on 10)

The memory device of claim 10, wherein the operations comprise activations.

### Claim 16 (depends on 10)

The memory device of claim 10, wherein the refresh period comprises a base refresh interval.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein the memory device is configured to be refreshed less often than every base refresh interval.

### Claim 18 (depends on 10)

The memory device of claim 10, wherein the circuitry is further configured to maintain the determined number of operations in a counter of the memory device.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein the circuitry is configured to reset the counter upon completion of the refresh period.

### Claim 20 (depends on 10)

The memory device of claim 10, wherein the circuitry is further configured to schedule the extra non-periodic refresh operation for the memory location in response to a determination that a refresh rate multiplier of the memory device is below a predetermined threshold value.

### Claim 21

A system, comprising:
a memory device including a memory location; and
a memory controller operatively coupled to the memory device and configured to:
determine a number of operations corresponding to the memory location during a refresh period; and
schedule an extra non-periodic refresh operation for the memory location after the refresh period when the determined number of operations exceeds a predetermined threshold.