# US 2021/0280233 A1 · Memory device receiving data clock signals and operation method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280233 A1 - Document ID: US20210280233A1 - Status: Published application - Kind: A1 - Application number: 17/319,253 - Filed: 2021-05-13 - Published: 2021-09-09 - Earliest claimed: 2019-08-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: SEONGHEON YU; JOUNGYEAL KIM; DOOWON BONG - Web page: https://patentgrep.com/patent/US20210280233A1 ## CPC - G11C 7/109: {Control signal input circuits} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G06F 1/3209: Monitoring remote activity, e.g. over telephone lines or network connections - G11C 7/1093: {Input synchronization} - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory device includes a command decoder configured to receive a command, a data clock receiving circuit configured to receive a data clock signal, and a control logic configured to control the data clock receiving circuit based on the command decoded by the command decoder, and enable the data clock receiving circuit. The control logic enables the data clock receiving circuit in response to the memory device receiving a dynamic data clock command. The data clock receiving circuit is in an enabled state until a predetermined particular command is received. ## Claims ### Claim 1 A memory device comprising: a command decoder configured to receive a command; a data clock receiving circuit configured to receive a data clock signal; and a control logic configured to control the data clock receiving circuit based on the command decoded by the command decoder, and enable the data clock receiving circuit, wherein the control logic enables the data clock receiving circuit in response to the memory device receiving a dynamic data clock command, and the data clock receiving circuit is in an enabled state until a predetermined particular command is received. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the predetermined particular command comprises a sync-off command indicating a termination of synchronization between the data clock signal and a main clock signal. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the control logic is configured to disable the data clock receiving circuit in response to the memory device receiving the sync-off command. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the predetermined particular command comprises a pre-charge command related to a data operation of the memory device. ### Claim 5 (depends on 4) The memory device of claim 4, wherein the control logic is configured to disable the data clock receiving circuit in response to the memory device receiving the pre-charge command. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the predetermined particular command comprises a power-down-entry command indicating entry into a power-down mode of the memory device. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the control logic is configured to disable the data clock receiving circuit in response to the memory device receiving the power-down-entry command. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the data clock receiving circuit comprises a buffer configured to be turned on or turned off by control of the control logic, and to receive the data clock signal. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the control logic is configured to enable the data clock receiving circuit by turning on the buffer through a data clock receiving circuit enable signal having a first logic level, and to disable the data clock receiving circuit by turning off the buffer through the data clock receiving circuit enable signal having a second logic level. ### Claim 10 An operation method of a memory device, the operation method comprising: receiving a dynamic data clock command to cause a data clock receiving circuit to be in an enabled state until a predetermined particular command is received; enabling the data clock receiving circuit in response to the dynamic data clock command; receiving the predetermined particular command; and disabling the data clock receiving circuit in response to the predetermined particular command. ### Claim 11 (depends on 10) The operation method of claim 10, wherein the predetermined particular command comprises a sync-off command indicating termination of synchronization between a data clock signal and a main clock signal. ### Claim 12 (depends on 10) The operation method of claim 10, wherein the predetermined particular command comprises a pre-charge command related to a data operation of the memory device. ### Claim 13 (depends on 12) The operation method of claim 12, further comprising: receiving or transmitting data based on a data clock signal received through the data clock receiving circuit after the data clock receiving circuit is enabled, wherein the data clock receiving circuit is disabled in response to the predetermined particular command after the receiving or transmitting of the data is completed. ### Claim 14 (depends on 10) The operation method of claim 10, wherein the predetermined particular command comprises a power-down-entry command indicating entry into a power-down mode of the memory device. ### Claim 15 (depends on 10) The operation method of claim 10, wherein the data clock receiving circuit comprises a buffer configured to receive a data clock signal, and the data clock receiving circuit is disabled by turning off the buffer by a control logic. ### Claim 16 A memory device comprising: a plurality of memory ranks comprising a first memory rank and a second memory rank; a first pin through which a data clock signal is input from outside of the memory device; a data clock receiving circuit configured to receive the data clock signal input via the first pin; a second pin through which a command is input from outside of the memory device; and a control logic configured to control a data operation of the memory device based on the command input via the second pin, enable the data clock receiving circuit based on a first command input via the second pin, control data operations of the first memory rank and the second memory rank during an interval when the data clock receiving circuit is in an enabled state, and disable the data clock receiving circuit based on a second command input via the second pin, wherein the first command is a command that causes the data clock receiving circuit, after the data clock receiving circuit is enabled, to be maintained in an enabled state until the second command is input via the second pin. ### Claim 17 (depends on 16) The memory device of claim 16, wherein the control logic is configured to control a data operation of the first memory rank and the second memory rank according to a rank interleaving method. ### Claim 18 (depends on 17) The memory device of claim 17, wherein the second command comprises a pre-charge command related to a data operation of the second memory rank. ### Claim 19 (depends on 16) The memory device of claim 16, wherein the second command comprises a sync-off command directing a termination of synchronization between the data clock signal and a main clock signal. ### Claim 20 (depends on 16) The memory device of claim 16, wherein the second command comprises a power-down-entry command indicating entry into a power-down mode of the memory device.