# US 2021/0280230 A1 · Memory device

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- Number: US 2021/0280230 A1
- Document ID: US20210280230A1
- Status: Published application
- Kind: A1
- Application number: 17/330,828
- Filed: 2021-05-26
- Published: 2021-09-09
- Earliest claimed: 2019-06-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Minhee CHO; Woobin SONG; Hyunmog PARK; Sangkil LEE
- Web page: https://patentgrep.com/patent/US20210280230A1

## CPC

- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 14/0027: {and the nonvolatile element is a ferroelectric element}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/33: {the capacitor extending under the transistor}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/488: {Word lines}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 51/30: characterised by the memory core region
- H10B 51/40: characterised by the peripheral circuit region
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

## Claims

### Claim at position 1

-13. (canceled)

### Claim 14

A memory device, comprising:
a plurality of first memory cells, each of the plurality of first memory cells including:
a first gate structure embedded in a substrate,
a first active region adjacent to the first gate structure and having a first channel region,
a first gate insulating layer between the first gate structure and the first channel region, and
a capacitor connected to the first active region and extended in a direction perpendicular to a top surface of the substrate;
a plurality of second memory cells, each of the plurality of second memory cells including:
a second gate structure,
a second active region adjacent to the second gate structure and having a second channel region, and
a second gate insulating layer between the second gate structure and the second channel region, the second gate insulating layer including a ferroelectric material having a higher dielectric constant than the first gate insulating layer,
wherein the plurality of second memory cells are to store or erase data based on a polarization state of the second gate insulating layer; and
a plurality of transfer switches, each of the plurality of transfer switches including active regions connected to the first gate structure and the second gate structure.

### Claim 15 (depends on 14)

The memory device as claimed in claim 14, wherein the plurality of transfer switches shares a single transfer gate structure.

### Claim 16 (depends on 14)

The memory device as claimed in claim 14, further comprising a controller configured to turn on the plurality of transfer switches and store data, read in the plurality of first memory cells, in the plurality of second memory cells.

### Claim 17 (depends on 14)

The memory device as claimed in claim 14, wherein the second gate structure is embedded in the substrate and has a same configuration as the first gate structure.

### Claim 18 (depends on 14)

The memory device as claimed in claim 14, wherein the first gate insulating layer is below the first gate structure, and the second gate insulating layer is above the second gate structure.

### Claim 19

A memory device, comprising:
a first memory cell array including first memory cells having volatility;
a second memory cell array including second memory cells having non-volatility, each of the second memory cells having a size smaller than a size of each of the first memory cells;
transfer switches between the first memory cells and the second memory cells; and
a controller configured to turn on the transfer switches, read data of at least one of the first memory cells, and store the data in at least one of the second memory cells.

### Claim 20 (depends on 19)

The memory device as claimed in claim 19, wherein a height of the first memory cells is greater than a height of the second memory cells in a direction perpendicular to a top surface of a substrate in which the first memory cells and the second memory cells are disposed.

### Claim at position 9

-25. (canceled)