# US 2021/0280225 A1 · Multiple concurrent modulation schemes in a memory system

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- Number: US 2021/0280225 A1
- Document ID: US20210280225A1
- Status: Published application
- Kind: A1
- Application number: 17/212,708
- Filed: 2021-03-25
- Published: 2021-09-09
- Earliest claimed: 2017-10-02
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Robert Nasry Hasbun; Timothy M. Hollis; Jeffrey P. Wright; Dean D. Gans
- Web page: https://patentgrep.com/patent/US20210280225A1

## CPC

- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G06F 1/3234: Power saving characterised by the action undertaken
- G06F 13/1684: {using multiple buses}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation
- G06F 13/4234: {being a memory bus}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2253: {Address circuits or decoders}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

## Claims

### Claim 1

(canceled)

### Claim 2

An apparatus, comprising:
a controller configured to communicate a first data and a second data;
a first signal path coupled with the controller and a memory die and configured to communicate the first data, wherein the controller is configured to select the first signal path based at least in part on a first chip enable response; and
a second signal path coupled with the controller and the memory die and configured to communicate the second data, wherein the controller is configured to select the second signal path based at least in part on a second chip enable response.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein:
the first chip enable response is associated with a binary signal; and
the second chip enable response is associated with a non-binary signal.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein:
the first data is associated with a first modulation scheme; and
the second data is associated with a second modulation scheme different than the first modulation scheme.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein:
the first modulation scheme is a non-return to zero (NRZ) modulation scheme; and
the second modulation scheme is a pulse amplitude modulation (PAM) modulation scheme.

### Claim 6 (depends on 2)

The apparatus of claim 2, wherein the first data and the second data are communicated concurrently.

### Claim 7 (depends on 2)

The apparatus of claim 2, wherein at least a first portion of the first data and a second portion of the second data are communicated concurrently.

### Claim 8 (depends on 2)

The apparatus of claim 2, wherein:
the first signal path comprises a first conductive path in a through silicon via (TSV) that is dedicated to communicating signals in response to the first chip enable response; and
the second signal path comprises a second conductive path in a TSV that is dedicated to communicating signals in response to the second chip enable response.

### Claim 9 (depends on 2)

The apparatus of claim 2, wherein the first data comprises metadata or control data, and wherein the second data comprises a different type of data than the first data.

### Claim 10 (depends on 2)

The apparatus of claim 2, wherein the first data or the second data comprise data associated with one or more memory cells of the memory die.

### Claim 11

An apparatus, comprising:
a controller configured to communicate a first data and a second data;
a first memory die;
a second memory die;
a first signal path coupled with the controller and the first memory die and configured to communicate the first data, wherein the controller is configured to select the first signal path based at least in part on a first chip enable response from the first memory die; and
a second signal path coupled with the controller and the second memory die and configured to communicate the second data, wherein the controller is configured to select the second signal path based at least in part on a second chip enable response from the second memory die.

### Claim 12 (depends on 11)

The apparatus of claim 11, further comprising:
a third signal path coupled with the controller and the first memory die and configured to communicate the second data; and
a fourth signal path coupled with the controller and the second memory die and configured to communicate the first data.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein:
the controller is configured to select the third signal path based at least in part on a third chip enable response from the first memory die; and
the controller is configured to select the fourth signal path based at least in part on a fourth chip enable response from the second memory die.

### Claim 14 (depends on 11)

The apparatus of claim 11, further comprising:
a bus coupled with the controller, the first memory die, and the second memory die, the bus configured to communicate the first data and the second data based on a timing of a system clock of the controller.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the bus is configured to communicate the first data during a rising edge, a falling edge, or both of the system clock.

### Claim 16 (depends on 11)

The apparatus of claim 11, wherein the first memory die comprises a different type of memory cells than the second memory die.

### Claim 17 (depends on 11)

The apparatus of claim 11, further comprising:
a first encoder coupled with the controller and configured to modulate the first data; and
a second encoder coupled with the controller and configured to modulate the second data.

### Claim 18 (depends on 11)

The apparatus of claim 11, wherein at least a first portion of the first data and a second portion of the second data are communicated concurrently.

### Claim 19

A method, comprising:
modulating, using a first modulation scheme, first data to be communicated to a memory die;
modulating, using a second modulation scheme, second data to be communicated to the memory die; and
transmitting the first data to the memory die using a first signal path based at least in part on receiving a first chip enable response from the memory die and the second data to the memory die using a second signal path based at least in part on receiving a second chip enable response from the memory die.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
receiving, from a host device, a command for accessing the memory die;
transmitting, to the memory die, a first chip enable signal based at least in part on receiving the command, wherein modulating the first data is based at least in part on transmitting the first chip enable signal.

### Claim 21 (depends on 19)

The method of claim 19, further comprising:
modulating, using the first modulation scheme, third data to be communicated to a second memory die;
modulating, using the second modulation scheme, fourth data to be communicated to the second memory die; and
transmitting the third data to the second memory die using a third signal path and the fourth data to the second memory die using a fourth signal path that is different than the third signal path.