# US 2021/0279836 A1 · Dynamic allocation of cache based on instantaneous bandwidth consumption at computing devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0279836 A1 - Document ID: US20210279836A1 - Status: Published application - Kind: A1 - Application number: 17/206,565 - Filed: 2021-03-19 - Published: 2021-09-09 - Earliest claimed: 2017-04-21 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Kiran C. Veernapu; Mohammed Tameem; Altug Koker; Abhishek R. Appu - Web page: https://patentgrep.com/patent/US20210279836A1 ## CPC - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F 12/023: {Free address space management} - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 2212/1016: Performance improvement - G06F 2212/1048: Scalability - G06F 2212/455: Image or video data - G06F 2212/604: Details relating to cache allocation - G06T 2210/08: Bandwidth reduction - G06T 2210/52: Parallel processing - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients in accordance with the one or more bandwidth requirements. ## Claims ### Claim at position 1 1-20. (canceled) ### Claim 21 An apparatus comprising: one or more processors including a graphics processor; a memory for storage of data; a graphics cache associated with the graphics processor, wherein the one or more processors are to: monitor incoming ingress throughput demand for threads of a plurality of threads accessing the graphics cache, the graphics cache to support a plurality of ways; measure an average throughput for one or more thread of the plurality of threads over a plurality of intervals, each interval being a certain number of clocks in duration; determine an instantaneous cache bandwidth being consumed from the graphics cache by the one or more threads of the plurality of threads based at least in part upon the measured average throughput measurement for the one or more threads; and dynamically allocate one or more portions of the plurality of ways of the graphics cache to the one or more threads of the plurality of threads in accordance with the determined instantaneous cache bandwidth consumption. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the plurality of threads includes threads for one or more components of the apparatus seeking access to the graphics cache for processing of one or more workloads. ### Claim 23 (depends on 22) The apparatus of claim 22, further comprising a tag array hosted by the graphics cache to trigger and control the allocation of the one or more portions of the ways of the graphics cache to the one or more threads in response to one or more instructions. ### Claim 24 (depends on 21) The apparatus of claim 21, wherein the measurement of the average throughput is over an M number of intervals, wherein an interval includes N clocks, and wherein M and N are values greater than one. ### Claim 25 (depends on 24) The apparatus of claim 24, wherein values of M and N are programmable. ### Claim 26 (depends on 21) The apparatus of claim 21, wherein the one or more portions of the ways of the graphics cache are allocated to the one or more threads in real-time. ### Claim 27 (depends on 21) The apparatus of claim 21, wherein the one or more portions of the ways of the graphics cache are allocated to the one or more threads without requiring a software interruption. ### Claim 28 (depends on 21) The apparatus of claim 21, wherein each way of the plurality of ways extends to a plurality of sets of the graphics cache. ### Claim 29 (depends on 21) The apparatus of claim 21, wherein the graphics processor is co-located with an application processor on a common semiconductor package. ### Claim 30 A method comprising: monitoring incoming ingress throughput demand for threads of a plurality of threads accessing a graphics cache associated with a graphics processor, the graphics cache to support a plurality of ways; measuring an average throughput for one or more thread of the plurality of threads over a plurality of intervals, each interval being a certain number of clocks in duration; determining an instantaneous cache bandwidth being consumed from the graphics cache by the one or more threads of the plurality of threads based at least in part upon the measured average throughput measurement for the one or more threads; and dynamically allocating one or more portions of the plurality of ways of the graphics cache to the one or more threads of the plurality of threads in accordance with the determined instantaneous cache bandwidth consumption. ### Claim 31 (depends on 30) The method of claim 30, wherein the plurality of threads includes threads for one or more components seeking access to the graphics cache for processing of one or more workloads. ### Claim 32 (depends on 31) The method of claim 31, further comprising: triggering and controlling the allocation of the one or more portions of the ways of the graphics cache to the one or more threads utilizing a tag array hosted by the graphics cache in response to one or more instructions. ### Claim 33 (depends on 30) The method of claim 30, wherein the measurement of the average throughput is over an M number of intervals, wherein an interval includes N clocks, and wherein M and N are values greater than one. ### Claim 34 (depends on 33) The method of claim 33, wherein values of M and N are programmable. ### Claim 35 (depends on 30) The method of claim 30, wherein the one or more portions of the ways of the graphics cache are allocated to the one or more threads in real-time. ### Claim 36 At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising: monitoring incoming ingress throughput demand for threads of a plurality of threads accessing a graphics cache associated with a graphics processor, the graphics cache to support a plurality of ways; measuring an average throughput for one or more thread of the plurality of threads over a plurality of intervals, each interval being a certain number of clocks in duration; determining an instantaneous cache bandwidth being consumed from the graphics cache by the one or more threads of the plurality of threads based at least in part upon the measured average throughput measurement for the one or more threads; and dynamically allocating one or more portions of the plurality of ways of the graphics cache to the one or more threads of the plurality of threads in accordance with the determined instantaneous cache bandwidth consumption. ### Claim 37 (depends on 36) The non-transitory machine-readable medium of claim 36, wherein the plurality of threads includes threads for one or more components seeking access to the graphics cache for processing of one or more workloads. ### Claim 38 (depends on 37) The non-transitory machine-readable medium of claim 37, wherein the instructions further includes instructions for: triggering and controlling the allocation of the one or more portions of the ways of the graphics cache to the one or more threads utilizing a tag array hosted by the graphics cache in response to one or more instructions. ### Claim 39 (depends on 36) The non-transitory machine-readable medium of claim 36, wherein the measurement of the average throughput is over an M number of intervals, wherein an interval includes N clocks, and wherein M and N are values greater than one. ### Claim 40 (depends on 36) The non-transitory machine-readable medium of claim 36, wherein the one or more portions of the ways of the graphics cache are allocated to the one or more threads in real-time.