# US 2021/0279560 A1 · Mixed-signal dot product processor with single capacitor per multiplier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0279560 A1 - Document ID: US20210279560A1 - Status: Published application - Kind: A1 - Application number: 16/808,708 - Filed: 2020-03-04 - Published: 2021-09-09 - Earliest claimed: 2020-03-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Mingu Kang; Seyoung Kim; Seonghoon Woo - Web page: https://patentgrep.com/patent/US20210279560A1 ## CPC - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - H03M 1/466: {using switched capacitors} - G06G 7/16: for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} - G06F 2207/4814: Non-logic devices, e.g. operational amplifiers - G06N 3/065: Analogue means - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor. ## Claims ### Claim 1 A mixed-signal logic processor, comprising: a plurality of mixed-signal multiplier branches, each having a set of branch-dedicated switches and a single branch-dedicated capacitor; a common switch, the common switch being external and common to each of the plurality of mixed-signal multiplier branches; and a first shared branch-external capacitor and a second shared branch-external capacitor, the first and the second shared branch-external capacitors being external to and shared by each of the plurality of mixed-signal multiplier branches, wherein various settings of the set of switches and the common switch enable various modes of the mixed-signal logic processor. ### Claim 2 (depends on 1) The mixed-signal logic processor of claim 1, wherein each of the single branch-dedicated capacitor and the first and second shared branch-external capacitors have a respective first side connected to ground. ### Claim 3 (depends on 1) The mixed-signal logic processor of claim 1, wherein each of the first capacitor and the second capacitor having a respective first side connected to a respective side of the common switch and a respective second side connected to ground. ### Claim 4 (depends on 1) The mixed-signal logic processor of claim 1, wherein the mixed-signal logic processor is configured to compute a dot product between an analog value vector and a digital value vector. ### Claim 5 (depends on 4) The mixed-signal logic processor of claim 4, wherein the mixed-signal logic processor is comprised in a system having at least one sensor and a memory device, wherein the analog value vector is received from the at least one sensor and the digital value vector is received from the memory device. ### Claim 6 (depends on 4) The mixed-signal logic processor of claim 4, wherein the sample mode samples the analog value vector using the single branch-dedicated capacitor in each of the plurality of mixed-signal multiplier branches to store a sample value. ### Claim 7 (depends on 1) The mixed-signal logic processor of claim 1, wherein the single branch-dedicated capacitor in each of the plurality of mixed-signal multiplier branches is of a same size. ### Claim 8 (depends on 1) The mixed-signal logic processor of claim 1, wherein the set of branch-dedicated switches include a first switch and a second switch, each having a first side connected to one side of the single branch-dedicated capacitor, wherein another side of the first switch is connected to an input voltage, and the another side of the second switch bypasses the input voltage. ### Claim 9 (depends on 8) The mixed-signal logic processor of claim 8, wherein the set of branch-dedicated switches include a third switch having a first side connected to the one side of the branch-dedicated capacitor and a second side connected to a common node with respect to each of the plurality of mixed-signal multiplier branches. ### Claim 10 (depends on 1) The mixed-signal logic processor of claim 1, wherein capacitor-wise each of the plurality of mixed-signal multiplier branches include only the single branch-dedicated capacitor. ### Claim 11 (depends on 1) The mixed-signal logic processor of claim 1, wherein the various modes of the mixed-signal logic processor comprise a reset mode, a sample mode, a merge mode, and an accumulate mode. ### Claim 12 A method for forming mixed-signal logic processor, comprising: arranging a plurality of mixed-signal multiplier branches to each have a set of branch-dedicated switches and a single branch-dedicated capacitor; connecting a common switch external from and common to each of the plurality of mixed-signal multiplier branches; and sharing a first shared branch-external capacitor and a second shared branch-external capacitor by each of the plurality of mixed-signal multiplier branches, wherein various settings of the set of switches and the common switch enable various modes of the mixed-signal logic processor. ### Claim 13 (depends on 12) The method of claim 12, further comprising connecting a respective first side of each of the single branch-dedicated capacitor and the first and the second shared branch-external capacitors to ground. ### Claim 14 (depends on 12) The method of claim 12, wherein the method further comprises: connecting a respective first side of each of the first capacitor and the second capacitor to a respective side of the common switch; and connecting a respective second side of each of the first capacitor and the second capacitor to ground. ### Claim 15 (depends on 12) The method of claim 12, further comprising configuring the mixed-signal logic processor to compute a dot product between an analog value vector and a digital value vector. ### Claim 16 (depends on 15) The method of claim 15, wherein the mixed-signal logic processor is comprised in a system having at least one sensor and a memory device, and wherein the method further comprising receiving the analog value vector from the at least one sensor and receiving the digital value vector from the memory device. ### Claim 17 (depends on 15) The method of claim 15, further comprising configuring the sample mode to sample the analog value vector using the single branch-dedicated capacitor in each of the plurality of mixed-signal multiplier branches to store a sample value. ### Claim 18 (depends on 12) The method of claim 12, further comprising forming the single branch-dedicated capacitor in each of the plurality of mixed-signal multiplier branches to be a same size. ### Claim 19 (depends on 12) The method of claim 12, wherein the set of branch-dedicated switches include a first switch and a second switch, and the method further comprises: connecting a first side of the first switch and the second switch to one side of the single branch-dedicated capacitor; connecting a second side of the first switch is connected to an input voltage; and bypassing the input voltage by a seconds side of the second switch. ### Claim 20 A computer processing system, comprising: a mixed-signal logic processor, wherein the mixed-signal logic processor comprises: a plurality of mixed-signal multiplier branches, each having a set of branch-dedicated switches and a single branch-dedicated capacitor; a common switch, the common switch being external and common to each of the plurality of mixed-signal multiplier branches; and a first shared branch-external capacitor and a second shared branch-external capacitor, the first and the second shared branch-external capacitors being external to and shared by each of the plurality of mixed-signal multiplier branches, and wherein various settings of the set of switches and the common switch enable various modes of the mixed-signal logic processor.