Hybrid analog-digital matrix processors
AssigneeLightmatter, Inc.
InventorsTYLER J. KENNEY, Martin B.Z. Forsythe, Tomo Lazovich, Darius Bunandar
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Abstract
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Claims21
An accelerator comprising:
- an analog processor arranged to perform matrix-vector multiplication and comprising inputs and outputs;
- a plurality of n-bit analog-to-digital converters (ADCs) coupled to respective outputs of the analog processor, where n is equal to or less than 16;
- and
- a plurality of analog amplifiers coupled to the analog processor.
A method for performing matrix-vector multiplication, comprising:
- generating a plurality of input analog signals based on a data vector;
- setting a gain of at least one of a plurality of multiplication units;
- controlling an analog processor based on a set of parameters representing a matrix;
- generating a plurality of output analog signals based on the plurality of input analog signals and the set of parameters;
- with the plurality of multiplication units, generating a plurality of scaled output analog signals by scaling the plurality of input analog signals and/or the plurality of output analog signals;
- and
- controlling a plurality of n-bit analog-to-digital converters (ADCs), where n is equal to or less than 16, to digitize the plurality of scaled output analog signals.
Dependencies are inferred from the claim text.