# US 2021/0279345 A1 · Data transmission method and apparatus in tee systems

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- Number: US 2021/0279345 A1
- Document ID: US20210279345A1
- Status: Published application
- Kind: A1
- Application number: 17/315,866
- Filed: 2021-05-10
- Published: 2021-09-09
- Earliest claimed: 2019-07-16
- Assignees: Advanced New Technologies Co., Ltd.
- Applicants: Advanced New Technologies Co., Ltd.
- Inventors: Qi Liu; Boran Zhao; Ying Yan; Changzheng Wei
- Web page: https://patentgrep.com/patent/US20210279345A1

## CPC

- G06F 12/1441: {for a range}
- G06F 21/606: {by securing the transmission between two devices or processes}
- G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing}
- G06F 12/0646: {Configuration or reconfiguration}
- G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow}
- G06F 2212/1016: Performance improvement
- G06F 2212/1052: Security improvement
- G06F 2221/2149: Restricted operating environment
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Examples of a data transmission method and apparatus in TEE systems are described. One example of the method includes: obtaining first data; obtaining a write offset address by reading a first address; obtaining a read offset address by reading a second address; determining whether the number of bytes in the first data is less than or equal to the number of writable bytes, where the number of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte; when the number of bytes in the first data is less than or equal to the number of writable bytes, writing the first data into third addresses starting from the write offset address; and updating the write offset address in the first address.

## Claims

### Claim 1

A computer-implemented method for exchanging data in a trusted execution environment (TEE) system, comprising:
obtaining data by a thread running on a TEE side of the TEE system, wherein the TEE system also comprises a non-TEE side and a shared memory, the shared memory comprising a first address, a second address, and multiple consecutive third addresses;
obtaining, by the thread, a write offset address by reading the first address, the write offset address indicating a writable start address in the multiple consecutive third addresses;
obtaining, by the thread, a read offset address by reading the second address, the read offset address indicating a readable start address in the multiple consecutive third addresses;
determining, by the thread, whether a number of bytes in the data is less than or equal to a number of writable bytes, wherein the number of writable bytes is determined based on the write offset address and the read offset address, and wherein each address corresponds to one byte; and
in response to determining that the number of bytes in the data is less than or equal to the number of writable bytes, writing, by the thread, the data into at least a portion of the multiple consecutive third addresses starting from the write offset address.

### Claim 2 (depends on 1)

The computer-implemented method of claim 1, further comprising:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, waiting until the number of bytes in the data is less than or equal to the number of writable bytes.

### Claim 3 (depends on 1)

The computer-implemented method of claim 1, wherein the shared memory further comprises a fourth address that stores a quantity of discarded data, and wherein the method further comprises:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, discarding the data; and
increasing the quantity of discarded data stored in the fourth address by one.

### Claim 4 (depends on 3)

The computer-implemented method of claim 3, wherein the quantity of discarded data is an atomic variable.

### Claim 5 (depends on 1)

The computer-implemented method of claim 1, wherein the write offset address is before the read offset address in the shared memory, and wherein the number of writable bytes is equal to a difference between the read offset address and the write offset address.

### Claim 6 (depends on 1)

The computer-implemented method of claim 1, wherein the write offset address is after the read offset address in the shared memory, wherein the number of writable bytes is equal to a difference between a number of the multiple consecutive third addresses and a number of non-writable bytes, and wherein the number of non-writable bytes is equal to a difference between the write offset address and the read offset address.

### Claim 7 (depends on 1)

The computer-implemented method of claim 1, wherein the write offset address is the same as the read offset address, and wherein the number of writable bytes is equal to a number of the multiple consecutive third addresses.

### Claim 8

A non-transitory, computer-readable medium storing one or more instructions that, when executed by a computer system of a trusted execution environment (TEE) system, cause the computer system to perform operations for exchanging data in the TEE system, wherein the operations comprise:
obtaining data by a thread running on a TEE side of the TEE system, wherein the TEE system also comprises a non-TEE side and a shared memory, the shared memory comprising a first address, a second address, and multiple consecutive third addresses;
obtaining, by the thread, a write offset address by reading the first address, the write offset address indicating a writable start address in the multiple consecutive third addresses;
obtaining, by the thread, a read offset address by reading the second address, the read offset address indicating a readable start address in the multiple consecutive third addresses;
determining, by the thread, whether a number of bytes in the data is less than or equal to a number of writable bytes, wherein the number of writable bytes is determined based on the write offset address and the read offset address, and wherein each address corresponds to one byte; and
in response to determining that the number of bytes in the data is less than or equal to the number of writable bytes, writing, by the thread, the data into at least a portion of the multiple consecutive third addresses starting from the write offset address.

### Claim 9 (depends on 8)

The non-transitory, computer-readable medium of claim 8, wherein the operations further comprise:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, waiting until the number of bytes in the data is less than or equal to the number of writable bytes.

### Claim 10 (depends on 8)

The non-transitory, computer-readable medium of claim 8, wherein the shared memory further comprises a fourth address that stores a quantity of discarded data, and wherein the operations further comprise:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, discarding the data; and
increasing the quantity of discarded data stored in the fourth address by one.

### Claim 11 (depends on 10)

The non-transitory, computer-readable medium of claim 10, wherein the quantity of discarded data is an atomic variable.

### Claim 12 (depends on 8)

The non-transitory, computer-readable medium of claim 8, wherein the write offset address is before the read offset address in the shared memory, and wherein the number of writable bytes is equal to a difference between the read offset address and the write offset address.

### Claim 13 (depends on 8)

The non-transitory, computer-readable medium of claim 8, wherein the write offset address is after the read offset address in the shared memory, wherein the number of writable bytes is equal to a difference between a number of the multiple consecutive third addresses and a number of non-writable bytes, and wherein the number of non-writable bytes is equal to a difference between the write offset address and the read offset address.

### Claim 14 (depends on 8)

The non-transitory, computer-readable medium of claim 8, wherein the write offset address is the same as the read offset address, and wherein the number of writable bytes is equal to a number of the multiple consecutive third addresses.

### Claim 15

A computer-implemented system, comprising:
one or more computers of a trusted execution environment (TEE) system; and
one or more computer memory devices interoperably coupled with the one or more computers and having tangible, non-transitory, machine-readable media storing one or more instructions that, when executed by the one or more computers, cause the one or more computers to perform one or more operations for exchanging data in the TEE system, wherein the operations comprise:
obtaining data by a thread running on a TEE side of the TEE system, wherein the TEE system also comprises a non-TEE side and a shared memory, the shared memory comprising a first address, a second address, and multiple consecutive third addresses;
obtaining, by the thread, a write offset address by reading the first address, the write offset address indicating a writable start address in the multiple consecutive third addresses;
obtaining, by the thread, a read offset address by reading the second address, the read offset address indicating a readable start address in the multiple consecutive third addresses;
determining, by the thread, whether a number of bytes in the data is less than or equal to a number of writable bytes, wherein the number of writable bytes is determined based on the write offset address and the read offset address, and wherein each address corresponds to one byte; and
in response to determining that the number of bytes in the data is less than or equal to the number of writable bytes, writing, by the thread, the data into at least a portion of the multiple consecutive third addresses starting from the write offset address.

### Claim 16 (depends on 15)

The computer-implemented system of claim 15, wherein the operations further comprise:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, waiting until the number of bytes in the data is less than or equal to the number of writable bytes.

### Claim 17 (depends on 15)

The computer-implemented system of claim 15, wherein the shared memory further comprises a fourth address that stores a quantity of discarded data, and wherein the operations further comprise:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, discarding the data; and
increasing the quantity of discarded data stored in the fourth address by one.

### Claim 18 (depends on 17)

The computer-implemented system of claim 17, wherein the quantity of discarded data is an atomic variable.

### Claim 19 (depends on 15)

The computer-implemented system of claim 15, wherein the write offset address is before the read offset address in the shared memory, and wherein the number of writable bytes is equal to a difference between the read offset address and the write offset address.

### Claim 20 (depends on 15)

The computer-implemented system of claim 15, wherein the write offset address is after the read offset address in the shared memory, wherein the number of writable bytes is equal to a difference between a number of the multiple consecutive third addresses and a number of non-writable bytes, and wherein the number of non-writable bytes is equal to a difference between the write offset address and the read offset address.

### Claim 21 (depends on 15)

The computer-implemented system of claim 15, wherein the write offset address is the same as the read offset address, and wherein the number of writable bytes is equal to a number of the multiple consecutive third addresses.
