# US 2021/0279104 A1 · High bandwidth connection between processor dies

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0279104 A1
- Document ID: US20210279104A1
- Status: Published application
- Kind: A1
- Application number: 17/205,905
- Filed: 2021-03-18
- Published: 2021-09-09
- Earliest claimed: 2017-04-17
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: ALTUG KOKER; Abhishek R. Appu; Kiran C. Veernapu; Joydeep Ray; Balaji Vembu
- Web page: https://patentgrep.com/patent/US20210279104A1

## CPC

- G06F 9/505: {considering the load}
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/5055: {considering software capabilities, i.e. software resources associated or available to the machine}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

An apparatus, comprising:
at least one processing unit (PU) disposed on a first PU die;
at least a first graphics processing unit (GPU) disposed on a first GPU die and a second graphics processing unit (GPU) disposed on a second GPU die; and
a communication network to provide communication connections between the first CPU die and the and the first GPU die;
the processing unit to:
receive graphics metadata from an application which is to execute on the at least one PU, wherein the graphics metadata indicates a level of graphics processing activity associated with the application;
determine, from the graphics metadata, an amount of graphics processing resources to be dedicated to the application, the graphics processing resources comprising a plurality of graphics processing units located on the first GPU and the second GPU;
configure one or more communication connections between the PU and the first GPU and the PU and the second GPU;
transmit the graphics data for the application from the PU to the plurality of graphics processing units via the communication network;
receive a completion acknowledgment from the plurality of graphics processing units; and
in response to a determination that the workload is finished, to terminate one or more communication connections on the communication network.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein:
the first GPU and the second GPU are positioned on a single layer of a semiconductor device.

### Claim 23 (depends on 22)

apparatus of claim 22, wherein:
the communication network traverses between the first GPU and the second GPU in the semiconductor device.

### Claim 24 (depends on 22)

The apparatus of claim 22, wherein:
the first PU is positioned in the planar configuration with the first GPU and the second GPU.

### Claim 25 (depends on 22)

The apparatus of claim 22, wherein:
the communication network traverses between the first PU and the first GPU and the second GPU in the semiconductor device.

### Claim 26 (depends on 26)

The apparatus of claim 26, wherein:
the first PU and the first GPU and the second GPU are disposed on a first layer of the semiconductor device; and
the communication network traverses between the first PU and the first GPU and the second GPU on the first layer of the semiconductor package.

### Claim 27

An electronic device, comprising:
a printed circuit board;
an input/output (I/O) module on the printed circuit board to provide an interface to a compute system;
an apparatus mounted on the printed circuit board and comprising:
at least one processing unit (PU) disposed on a first PU die;
at least a first graphics processing unit (GPU) disposed on a first GPU die and a second graphics processing unit (GPU) disposed on a second GPU die; and
a communication network to provide communication connections between the first CPU die and the and the first GPU die;
the processing unit to:
receive graphics metadata from an application which is to execute on the at least one PU, wherein the graphics metadata indicates a level of graphics processing activity associated with the application;
determine, from the graphics metadata, an amount of graphics processing resources to be dedicated to the application, the graphics processing resources comprising a plurality of graphics processing units located on the first GPU and the second GPU;
configure one or more communication connections between the PU and the first GPU and the PU and the second GPU;
transmit the graphics data for the application from the PU to the plurality of graphics processing units via the communication network;
receive a completion acknowledgment from the plurality of graphics processing units; and
in response to a determination that the workload is finished, to terminate one or more communication connections on the communication network.

### Claim 28 (depends on 27)

The electronic device of claim 27, wherein:
the first GPU and the second GPU are positioned on a single layer of a semiconductor device.

### Claim 29 (depends on 28)

The electronic device of claim 28, wherein:
the communication network traverses between the first GPU and the second GPU in the semiconductor device.

### Claim 30 (depends on 28)

The electronic device of claim 28, wherein:
the first PU is positioned in the planar configuration with the first GPU and the second GPU.

### Claim 31 (depends on 27)

The electronic device of claim 27, wherein:
the communication network traverses between the first PU and the first GPU and the second GPU in the semiconductor device.

### Claim 32 (depends on 31)

The electronic device of claim 31, wherein:
the first PU and the first GPU and the second GPU are disposed on a first layer of the semiconductor device; and
the communication network traverses between the first PU and the first GPU and the second GPU on the first layer of the semiconductor package.

### Claim 33

A method, comprising:
receiving graphics metadata from an application which is to execute on at least one processing unit (PU) disposed on a first die, wherein the graphics metadata indicates a level of graphics processing activity associated with the application;
determining, from the graphics metadata, an amount of graphics processing resources to be dedicated to the application, the graphics processing resources comprising a plurality of graphics processing units located on at least a first graphics processing unit (GPU) disposed on a first GPU die and a second graphics processing unit (GPU) disposed on a second GPU die, separate from the first GPU die;
configuring one or more communication connections in a communication network to provide communication connections between the PU and the first GPU and the first GPU and the second GPU;
transmitting the graphics data for the application from the CPU to the plurality of graphics processing units via the communication network;
receiving a completion acknowledgment from the plurality of graphics processing units; and
in response to a determination that the workload is finished, terminating one or more communication connections on the communication network.

### Claim 34 (depends on 33)

The method of claim 33, wherein:
the first GPU and the second GPU are positioned on a single layer of a semiconductor device.

### Claim 35 (depends on 34)

The method of claim 34, wherein:
the communication network traverses between the first GPU and the second GPU in the semiconductor device.

### Claim 36 (depends on 34)

The method of claim 34, wherein:
the PU is positioned in the planar configuration with the first GPU and the second GPU.

### Claim 37 (depends on 36)

The method of claim 36, wherein:
the communication network traverses between the PU and the first GPU and the second GPU in the semiconductor device.

### Claim 38 (depends on 37)

The method of claim 37, wherein:
the PU and the first GPU and the second GPU are disposed on a first layer of the semiconductor device; and
the communication network traverses between the PU and the first GPU and the second GPU on the first layer of the semiconductor package.