# US 2021/0279065 A1 · Lightweight memory ordering primitives > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0279065 A1 - Document ID: US20210279065A1 - Status: Published application - Kind: A1 - Application number: 16/808,346 - Filed: 2020-03-03 - Published: 2021-09-09 - Earliest claimed: 2020-03-03 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Nuwan Jayasena; Shaizeen Aga; Anirban Nag - Web page: https://patentgrep.com/patent/US20210279065A1 ## CPC - G06F 9/3834: {Maintaining memory consistency} - G06F 9/30087: {Synchronisation or serialisation instructions} - G06F 9/3842: {Speculative instruction execution} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques are provided for performing memory operations. The techniques include issuing, by a processor, a fence primitive to a memory system, the fence primitive issued in a manner that indicates a program order of memory operation execution. ## Claims ### Claim 1 A method for performing memory operations comprising: issuing, by a processor, a fence primitive to a memory system, the fence primitive issued in a manner that indicates a program order of memory operation execution. ### Claim 2 (depends on 1) The method of claim 1, further comprising: issuing a first set of memory operations and a second set of memory operations to the memory system, the second set of memory operations being younger than the first set of memory operations, wherein the fence primitive indicates relative program order of the first set of memory operations with respect to the fence and to the second set of memory operations. ### Claim 3 (depends on 2) The method of claim 2, wherein: the fence primitive is younger than the first set of memory operations; and the processor does not wait for an indication that the memory operations of the first set of memory operations are complete in the memory system before issuing the second set of memory operations to the memory system for execution. ### Claim 4 (depends on 2) The method of claim 2, wherein a phase of the memory system enforces ordering imposed by the fence primitive by preventing memory operations of the second set from appearing to software to execute before memory operations of the first set. ### Claim 5 (depends on 2) The method of claim 2, wherein a phase of the memory system issues the first set, the fence primitive, and the second set to a subsequent phase of the memory system in a manner that indicates program order of the fence primitive with respect to the first set and the second set. ### Claim 6 (depends on 2) The method of claim 2, wherein the fence primitive is issued with explicit information that indicates the execution order of the fence primitive with respect to the first set of memory operations. ### Claim 7 (depends on 6) The method of claim 6, wherein the explicit information comprises a group identification issued with the fence primitive, wherein the group identification identifies the first set as being older than the fence primitive. ### Claim 8 (depends on 7) The method of claim 7, wherein the operations of the first set are transmitted to the memory system with a group identification identifying the operations as part of a first group that is older than the fence primitive. ### Claim 9 (depends on 2) The method of claim 2, wherein the first set, the second set, and the fence primitive are issued to the memory system in an order that indicates that the first set is older than the fence primitive and that the second set is younger than the fence primitive. ### Claim 10 (depends on 2) The method of claim 2, wherein: a phase of the memory system comprises a branch point having two subsequent memory system phases; and the phase transmits the fence primitive to both of the two subsequent memory system phases. ### Claim 11 (depends on 10) The method of claim 10, wherein the memory system further comprises a branch reconvergence point configured to: receive the fence primitive from both of the two subsequent memory system phases; and execute the first set and the second set in order with respect to the fence primitive received from both of the two subsequent memory system phases. ### Claim 12 (depends on 1) The method of claim 1, wherein the fence primitive specifies a last phase of the memory system that enforces the ordering of the fence primitive. ### Claim 13 A system, comprising: a processor; and a memory system, wherein the processor is configured to: issue a fence primitive to the memory system, the fence primitive issued in a manner that indicates a program order of memory operation execution. ### Claim 14 (depends on 13) The system of claim 13, wherein the processor is further configured to: issue a first set of memory operations and a second set of memory operations to the memory system, the second set of memory operations being younger than the first set of memory operations, wherein the fence primitive indicates relative program order of the first set of memory operations with respect to the fence and to the second set of memory operations. ### Claim 15 (depends on 14) The system of claim 14, wherein: the fence primitive is younger than the first set of memory operations; and the processor is configured not to wait for an indication that the memory operations of the first set of memory operations are complete in the memory system before issuing the second set of memory operations to the memory system for execution. ### Claim 16 (depends on 14) The system of claim 14, wherein a phase of the memory system enforces ordering imposed by the fence primitive by preventing memory operations of the second set from appearing to software to execute before memory operations of the first set. ### Claim 17 (depends on 14) The system of claim 14, wherein a phase of the memory system issues the first set, the fence primitive, and the second set to a subsequent phase of the memory system in a manner that indicates program order of the fence primitive with respect to the first set and the second set. ### Claim 18 (depends on 14) The system of claim 14, wherein the fence primitive is issued with explicit information that indicates the execution order of the fence primitive with respect to the first set of one or more memory operations. ### Claim 19 (depends on 18) The system of claim 18, wherein the explicit information comprises a group identification issued with the fence primitive, wherein the group identification identifies the first set as being older than the fence primitive. ### Claim 20 (depends on 19) The system of claim 19, wherein the operations of the first set are transmitted to the memory system with a group identification identifying the operations as part of a first group that is older than the fence primitive. ### Claim 21 (depends on 14) The system of claim 14, wherein the first set, the second set, and the fence primitive are issued to the memory system in an order that indicates that the first set is older than the fence primitive and that the second set is younger than the fence primitive. ### Claim 22 (depends on 14) The system of claim 14, wherein: a phase of the memory system comprises a branch point having two subsequent memory system phases; and the phase transmits the fence primitive to both of the two subsequent memory system phases. ### Claim 23 (depends on 22) The system of claim 22, wherein the memory system further comprises a branch reconvergence point configured to: receive the fence primitive from both of the two subsequent memory system phases; and execute the first set and the second set in order with respect to the fence primitive received from both of the two subsequent memory system phases. ### Claim 24 (depends on 13) The system of claim 13, wherein the fence primitive specifies a last phase of the memory system that enforces the ordering of the fence primitive. ### Claim 25 A processor, configured to: issue a fence primitive to a memory system, the fence primitive issued in a manner that indicates a program order of memory operation execution. ### Claim 26 (depends on 25) The processor of claim 25, further configured to: issue a first set of memory operations and a second set of memory operations to the memory system, the second set of memory operations being younger than the first set of memory operations, wherein the fence primitive indicates relative program order of the first set of memory operations with respect to the fence and to the second set of memory operations. ### Claim 27 (depends on 26) The processor of claim 26, wherein: the fence primitive is younger than the first set of memory operations; and the processor is configured not to wait for an indication that the memory operations of the first set of memory operations are complete in the memory system before issuing the second set of memory operations to the memory system for execution. ### Claim 28 (depends on 26) The processor of claim 26, wherein the fence primitive is issued with explicit information that indicates the execution order of the fence primitive with respect to the first set of one or more memory operations. ### Claim 29 (depends on 28) The processor of claim 28, wherein the explicit information comprises a group identification issued with the fence primitive, wherein the group identification identifies the first set as being older than the fence primitive. ### Claim 30 (depends on 29) The processor of claim 29, wherein the operations of the first set are transmitted to the memory system with a group identification identifying the operations as part of a first group that is older than the fence primitive. ### Claim 31 (depends on 26) The processor of claim 26, wherein the first set, the second set, and the fence primitive are issued to the memory system in an order that indicates that the first set is older than the fence primitive and that the second set is younger than the fence primitive.