# US 2021/0279005 A1 · Memory circuit, information processing circuit, and information processing apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0279005 A1 - Document ID: US20210279005A1 - Status: Published application - Kind: A1 - Application number: 17/184,218 - Filed: 2021-02-24 - Published: 2021-09-09 - Earliest claimed: 2020-03-04 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Zheye WANG; Akiyuki KANEKO - Web page: https://patentgrep.com/patent/US20210279005A1 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 2212/7202: Allocation control and policies - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one embodiment, a memory circuit includes a plurality of nonvolatile memory cells and a control circuit. Each of the plurality of nonvolatile memory cells loses stored data when the stored data is read. The control circuit reads data from a first memory cell among the plurality of memory cells as designated by a first instruction but does not write the data read from the first memory cell back to the first memory cell after the first instruction is received. The control circuit reads data from a second memory cell among the plurality of memory cells as designated by a second instruction and writes the data read from the second memory cell back to the second memory cell after the second instruction is received. ## Claims ### Claim 1 A memory circuit, comprising: a plurality of nonvolatile memory cells each of which loses stored data when read; and a control circuit configured to: receive a first instruction, then read data from a first memory cell designated by the first instruction but not rewrite the read data back to the first memory cell, and receive a second instruction, then read data from a second memory cell designated by the second instruction and rewrite the read data back to the second memory cell. ### Claim 2 (depends on 1) The memory circuit according to claim 1, wherein the first instruction is a first command type, and the second instruction is a second command type different from the first command type. ### Claim 3 (depends on 1) The memory circuit according to claim 1, wherein the first instruction includes a read command and a non-write back instruction, and the second instruction includes a read command and a write-back instruction. ### Claim 4 (depends on 3) The memory circuit according to claim 3, wherein the control circuit further includes a first terminal that receives the non-write back instruction and the write-back instruction. ### Claim 5 (depends on 1) The memory circuit according to claim 1, wherein the physical address of the first memory cell is the same as the physical address of the second memory cell. ### Claim 6 (depends on 1) The memory circuit according to claim 1, wherein the physical address of the first memory cell is different from the physical address of the second memory cell. ### Claim 7 (depends on 6) The memory circuit according to claim 6, wherein the first instruction includes a read command and first address information, and a second instruction includes a read command and second address information. ### Claim 8 An information processing circuit, comprising: a memory circuit including a plurality of nonvolatile memory cells, each of which loses stored data when stored data is read therefrom, wherein the memory circuit is configured to: read data from a first memory cell in the plurality of nonvolatile memory cells when the first memory cell is designated by a first instruction received by the memory circuit, but not rewrite the data back to first memory cell after the first memory cell has been read, and read data from a second memory cell in the plurality of nonvolatile memory cells when the second memory cell is designated by a second instruction received by the memory circuit and rewrite the data back to the second memory cell after the second memory cell has been read. ### Claim 9 (depends on 8) The information processing circuit according to claim 8, wherein the first instruction includes a first command, and the second instruction includes a second command different from the first command. ### Claim 10 (depends on 8) The information processing circuit according to claim 8, wherein the first instruction includes a read command and first information that does not include a write instruction, and the second instruction includes a read command and second information that includes a write instruction. ### Claim 11 (depends on 10) The information processing circuit according to claim 10, further comprising: a first terminal that outputs the first information and the second information. ### Claim 12 (depends on 8) The information processing circuit according to claim 8, wherein the first memory cell has the same physical address as the second memory cell. ### Claim 13 (depends on 8) The information processing circuit according to claim 8, further comprising: a processor; a first circuit that transmits the first instruction and the second instruction; and a second circuit that instructs the first circuit to transmit the first instruction or the second instruction according to a first request from the processor. ### Claim 14 An information processing apparatus, comprising: a memory circuit including: a plurality of nonvolatile memory cells each of which loses stored data when read; and a control circuit configured to: receive a first instruction, then read data from a first memory cell designated by the first instruction but not rewrite the read data back to the first memory cell, and receive a second instruction, then read data from a second memory cell designated by the second instruction and rewrite the read data back to the second memory cell; and an information processing circuit configured to transmit the first instruction and the second instruction. ### Claim 15 (depends on 14) The information processing apparatus according to claim 14, wherein the first instruction includes a first command, and the second instruction includes a second command different from the first command. ### Claim 16 (depends on 14) The information processing apparatus according to claim 14, wherein the first instruction includes a read command and first information that does not include a write instruction, and the second instruction includes a read command and second information that includes a write instruction. ### Claim 17 (depends on 16) The information processing apparatus according to claim 16, wherein the memory circuit and the information processing circuit are connected to each other via a first signal line that transmits the first information and the second information. ### Claim 18 (depends on 14) The information processing apparatus according to claim 14, wherein the first memory cell has the same physical address as the second memory cell. ### Claim 19 (depends on 14) The information processing apparatus according to claim 14, wherein the physical address of the first memory cell is different from the physical address of the second memory cell. ### Claim 20 (depends on 19) The information processing apparatus according to claim 19, wherein the first instruction includes a read command and first address information, and the second instruction includes the read command and second address information different from the first address information.