# US 2021/0279004 A1 · Ssd system and ssd control system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0279004 A1 - Document ID: US20210279004A1 - Status: Published application - Kind: A1 - Application number: 17/153,894 - Filed: 2021-01-21 - Published: 2021-09-09 - Earliest claimed: 2020-03-03 - Assignees: Silicon Motion, Inc. - Applicants: Silicon Motion, Inc. - Inventors: Chih-Chien Lin; Hung-Pin Tsai; Chien-An Chen - Web page: https://patentgrep.com/patent/US20210279004A1 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device} - G06F 3/0658: {Controller construction arrangements} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 13/1668: {Details of memory controller} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An SSD control system comprising a first control system including a first control device, and comprising a second control system including a second control device. The first control system is coupled to a first SSD group comprising a plurality of first SSDs, and the second control system is coupled to a second SSD group comprising a plurality of second SSDs. The first control device comprises: a first processing circuit, configured to control a first portion of the first SSDs; and a second processing circuit, configured to control a second portion of the first SSDs. The second control device comprises: a first signal repeating device, configured to respectively receive first, second control signals from the first, second processing circuit to control a first, second portion of the second SSDs. The second control system does not comprise any circuit which can generate control signals to control the second SSD group. ## Claims ### Claim 1 An SSD control system, comprising: a first control system, coupled to a first SSD group (Solid state disk) comprising a plurality of first SSDs, comprising: a first control device, comprising: a first processing circuit, configured to control a first portion of the first SSDs; and a second processing circuit, configured to control a second portion of the first SSDs; a second control system, coupled to a second SSD group comprising a plurality of second SSDs, comprising: a second control device, comprising: a first signal repeating device, configured to receive first control signals generated by the first processing circuit to control a first portion of the second SSDs, and configured to receive second control signals generated by the second processing circuit to control a second portion of the second SSDs; wherein the second control system does not comprise any circuit which can generate control signals to control the second SSD group. ### Claim 2 (depends on 1) The SSD control system of claim 1, wherein first control system further comprises a third control device and the second control system further comprises a fourth control device, wherein the third control device comprises: a third processing circuit; and a fourth processing circuit, wherein the first processing circuit is replaced by the third processing circuit to control the first portion of the first SSDs when the first control device could not operate normally, wherein the second processing circuit is replaced by the fourth processing circuit to control the second portion of the first SSDs when the first control device could not operate normally; wherein the fourth control device comprises: a second signal repeating device, configured to receive third control signals generated by the third processing circuit to control the first portion of the second SSDs, and configured to receive fourth control signals generated by the fourth processing circuit to control the second portion of the second SSDs. ### Claim 3 (depends on 2) The SSD control system of claim 2, wherein the first processing circuit, the second processing circuit, the third processing circuit and the fourth processing circuit are CPUs; wherein the first processing circuit, the second processing circuit are provided on a first mother board, and the third processing circuit, the fourth processing circuit are provided on a second mother board. ### Claim 4 (depends on 2) The SSD control system of claim 2, wherein the first portion of the first SDDs are odd-numbered SSD among the first SSDs and the second portion of the first SDDs are even-numbered SSD among the first SSDs; wherein the first portion of the second SDDs are odd-numbered SSD among the second SSDs and the second portion of the second SDDs are even-numbered SSD among the second SSDs. ### Claim 5 (depends on 1) The SSD control system of claim 1, wherein the first control device and the second control device comprise PCIe (Peripheral Component Interconnect Express) interfaces, and the first signal repeating device receives the first control signals and the second control signals via the PCIe interfaces. ### Claim 6 (depends on 1) The SSD control system of claim 1, wherein the first control device and the second control device respectively comprises a BMC (Board Management Controller) to monitor control device information; wherein the first control device and the second control device respectively comprises a first port configured to transmit and receive the first control signals and the second control signals; wherein the first control device and the second control device respectively comprises a second port configured to transmit or to receive the monitor control device information. ### Claim 7 (depends on 1) The SSD control system of claim 1, wherein the first portion of the first SDDs are odd-numbered SSD among the first SSDs and the second portion of the first SDDs are even-numbered SSD among the first SSDs; wherein the first portion of the second SDDs are odd-numbered SSD among the second SSDs and the second portion of the second SDDs are even-numbered SSD among the second SSDs. ### Claim 8 (depends on 1) The SSD control system of claim 1, comprising: a first case, wherein the first control system and the first SSDs are provided in the first case; and a second case, coupled to the first case via at least one port, wherein the second control system and the second SSDs are provided in the second case. ### Claim 9 (depends on 8) The SSD control system of claim 8, comprising: wherein the first SSDs can be connected to or disconnected from from the first control system by hot plugging; wherein the second SSDs can be connected to or disconnected from the second control system by hot plugging. ### Claim 10 (depends on 8) The SSD control system of claim 8, wherein the first control system and the second control system are stacked. ### Claim 11 An SSD system, comprising: a first SSD group (Solid state disk) comprising a plurality of first SSDs; a second SSD group comprising a plurality of second SSDs; a first control system, coupled to the first SSD, comprising: a first control device, comprising: a first processing circuit, configured to control a first portion of the first SSDs; and a second processing circuit, configured to control a second portion of the first SSDs; a second control system, coupled to the second SSD, comprising: a second control device, comprising: a first signal repeating device, configured to receive first control signals generated by the first processing circuit to control a first portion of the second SSDs, and configured to receive second control signals generated by the second processing circuit to control a second portion of the second SSDs; wherein the second control system does not comprise any circuit which can generate control signals to control the second SSD group. ### Claim 12 (depends on 11) The SSD system of claim 11, wherein first control system further comprises a third control device and the second control system further comprises a fourth control device, wherein the third control device comprises: a third processing circuit; and a fourth processing circuit, wherein the first processing circuit is replaced by the third processing circuit to control the first portion of the first SSDs when the first control device could not operate normally, wherein the second processing circuit is replaced by the fourth processing circuit to control the second portion of the first SSDs when the first control device could not operate normally; wherein the fourth control device comprises: a second signal repeating device, configured to receive third control signals generated by the third processing circuit to control the first portion of the second SSDs, and configured to receive fourth control signals generated by the fourth processing circuit to control the second portion of the second SSDs. ### Claim 13 (depends on 12) The SSD system of claim 12, wherein the first processing circuit, the second processing circuit, the third processing circuit and the fourth processing circuit are CPUs; wherein the first processing circuit, the second processing circuit are provided on a first mother board, and the third processing circuit, the fourth processing circuit are provided on a second mother board. ### Claim 14 (depends on 12) The SSD system of claim 12, wherein the first portion of the first SDDs are odd-numbered SSD among the first SSDs and the second portion of the first SDDs are even-numbered SSD among the first SSDs; wherein the first portion of the second SDDs are odd-numbered SSD among the second SSDs and the second portion of the second SDDs are even-numbered SSD among the second SSDs. ### Claim 15 (depends on 11) The SSD system of claim 11, wherein the first control device and the second control device comprise PCIe (Peripheral Component Interconnect Express) interfaces, and the first signal repeating device receives the first control signals and the second control signals via the PCIe interfaces. ### Claim 16 (depends on 11) The SSD system of claim 11, wherein the first control device and the second control device respectively comprises a BMC (Board Management Controller) to monitor control device information; wherein the first control device and the second control device respectively comprises a first port configured to transmit and receive the first control signals and the second control signals; wherein the first control device and the second control device respectively comprises a second port configured to transmit or to receive the monitor control device information. ### Claim 17 (depends on 11) The SSD system of claim 11, wherein the first portion of the first SDDs are odd-numbered SSD among the first SSDs and the second portion of the first SDDs are even-numbered SSD among the first SSDs; wherein the first portion of the second SDDs are odd-numbered SSD among the second SSDs and the second portion of the second SDDs are even-numbered SSD among the second SSDs. ### Claim 18 (depends on 11) The SSD system of claim 11, comprising: a first case, wherein the first control system and the first SSDs are provided in the first case; and a second case, coupled to the first case via at least one port, wherein the second control system and the second SSDs are provided in the second case. ### Claim 19 (depends on 18) The SSD system of claim 18, comprising: wherein the first SSDs can be connected to or disconnected from the first control system by hot plugging; wherein the second SSDs can be connected to or disconnected from the second control system by hot plugging. ### Claim 20 (depends on 18) The SSD system of claim 18, wherein the first control system and the second control system are stacked.