# US 2021/0278976 A1 · Coherency locking schemes

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- Number: US 2021/0278976 A1
- Document ID: US20210278976A1
- Status: Published application
- Kind: A1
- Application number: 16/809,058
- Filed: 2020-03-04
- Published: 2021-09-09
- Earliest claimed: 2020-03-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yun Li; John Traver
- Web page: https://patentgrep.com/patent/US20210278976A1

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.

## Claims

### Claim 1

A method, comprising:
receiving, at a controller for a memory sub-system, a first write command from a host device to write a first block of data at a first memory address of a memory device of the memory sub-system;
locking a first coherency of the first memory address responsive to receiving the first write command; and
receiving, from a processing core of the controller, a second write command to write a second block of data at a second memory address of the memory device, wherein a second coherency of the second memory address is maintained in an unlocked state after receiving the second write command.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
updating, responsive to completing the second write command, a mapping record to indicate the second block of data is located at the second memory address, wherein the mapping record indicates that the second block of data is located at a prior memory address prior to the updating.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
updating, responsive to receiving the first write command, the mapping record to indicate the first block of data is located at the first memory address.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
receiving a read command to read the first block of data; and
sending a coherency lock indication responsive to the read command.

### Claim 5 (depends on 2)

The method of claim 2, further comprising:
receiving, prior to the updating the mapping record for the second block of data, a read command to read the second block of data; and
reading the prior memory address to provide the second block of data.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first write command and the second write command are received at a first processing core of the controller, and the second write command is received from a second processing core of the controller.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second processing core of the controller executes a garbage collection procedure that generates the second write command.

### Claim 8 (depends on 1)

The method of claim 1, wherein the locking the first coherency comprises:
providing a coherency lock command and the first memory address to a coherency block of the controller.

### Claim 9

A system, comprising:
a plurality of memory components; and
a processing device operatively coupled with the plurality of memory components, the processing device to:
receive a first write command from a device that is external to the system, the first write command to write a first block of data at a first memory address of the plurality of memory components;
lock a first coherency of the first memory address responsive to receiving the first write command;
receive a second write command from a sub-component of the system, the second write command to write a second block of data at a second memory address of the plurality of memory components; and
maintain a second coherency of the second memory address in an unlocked state after receiving the second write command.

### Claim 10 (depends on 9)

The system of claim 9, further comprising:
the processing device further to:
update, responsive to completing the second write command, a mapping record to indicate the second block of data is located at the second memory address, wherein the mapping record indicates that the second block of data is located at a prior memory address prior to the update.

### Claim 11 (depends on 10)

The system of claim 10, further comprising:
the processing device further to:
update, responsive to receiving the first write command, the mapping record to indicate the first block of data is located at the first memory address.

### Claim 12 (depends on 11)

The system of claim 11, further comprising:
the processing device further to:
receive a read command to read the first block of data; and
send a coherency lock indication responsive to the read command.

### Claim 13 (depends on 10)

The system of claim 10, further comprising:
the processing device further to:
receive, prior to the update of the mapping record for the second block of data, a read command to read the second block of data; and
read the prior memory address to provide the second block of data.

### Claim 14 (depends on 9)

The system of claim 9, wherein the first write command and the second write command are received at a first processing core of the processing device, and the second write command is received from a second processing core of the processing device.

### Claim 15 (depends on 14)

The system of claim 14, wherein the second processing core executes a garbage collection procedure that generates the second write command.

### Claim 16

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a first write command from an external device to write a first block of data at a first memory address of a memory device;
lock a first coherency of the first memory address responsive to receiving the first write command; and
receive a second write command from an internal component of the processing device to write a second block of data at a second memory address of the memory device, wherein a second coherency of the second memory address remains in an unlocked state after receiving the second write command.

### Claim 17 (depends on 16)

The non-transitory computer-readable storage medium of claim 16, wherein the processing device is further to:
update, responsive to completing the second write command, a mapping record to indicate the second block of data is located at the second memory address, wherein the mapping record indicates that the second block of data is located at a prior memory address prior to the update.

### Claim 18 (depends on 17)

The non-transitory computer-readable storage medium of claim 17, wherein the processing device is further to:
update, responsive to the first write command, the mapping record to indicate the first block of data is located at the first memory address.

### Claim 19 (depends on 18)

The non-transitory computer-readable storage medium of claim 18, wherein the processing device is further to:
receive a read command to read the first block of data; and
send a coherency lock indication responsive to the read command.

### Claim 20 (depends on 17)

The non-transitory computer-readable storage medium of claim 17, wherein the processing device is further to:
receive, prior to the update of the mapping record for the second block of data, a read command to read the second block of data; and
read the prior memory address to provide the second block of data.