# US 2021/0278893 A1 · Power management integrated circuit based system management bus isolation

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- Number: US 2021/0278893 A1
- Document ID: US20210278893A1
- Status: Published application
- Kind: A1
- Application number: 17/327,282
- Filed: 2021-05-21
- Published: 2021-09-09
- Earliest claimed: 2019-07-29
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Matthew D. Rowley
- Web page: https://patentgrep.com/patent/US20210278893A1

## CPC

- G06F 1/3225: of memory devices
- G06F 1/3296: by lowering the supply or operating voltage
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3221: of disk drive devices
- G06F 1/3268: {Power saving in hard disk drive}
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 13/20: for access to input/output bus
- G06F 13/4081: {Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004)}
- G06F 2213/40: Bus coupling
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

## Claims

### Claim 1

A power management integrated circuit (PMIC) comprising:
a voltage supply input;
power management circuitry coupled to the voltage supply input and configured to determine a power mode;
a system management bus (SMB) input; and
a hot swap SMB controller coupled to the SMB input and the power management circuitry, the hot swap SMB controller configured to route, based on the power mode, data between the SMB input and an SMB output of multiple SMB outputs.

### Claim 2 (depends on 1)

The PMIC of claim 1, wherein the hot swap SMB controller is further configured to route address resolution protocol (ARP) communications between the SMB input and the multiple SMB outputs based on the power mode.

### Claim 3 (depends on 1)

The PMIC of claim 1, further comprising:
a first SMB controller coupled to the hot swap SMB controller and a first SMB output, the first SMB controller being configured to isolate the SMB input from the first SMB output based on the power mode.

### Claim 4 (depends on 3)

The PMIC of claim 3, further comprising:
a second SMB controller coupled to the hot swap SMB controller and a second SMB output, the second SMB controller being configured to isolate the SMB input from the second SMB output during a second power mode different from the power mode.

### Claim 5 (depends on 4)

The PMIC of claim 4, wherein the power management circuitry is configured to auto-detect a transition to the second power mode and to automatically isolate the second SMB output from the SMB input using the second SMB controller in response to the transition to the second power mode.

### Claim 6 (depends on 5)

The PMIC of claim 5, wherein:
the first SMB controller is configured by the hot swap SMB controller to communicate first SMB signals between the SMB input and the first SMB output during the second power mode; and
the second SMB controller is configured to communicate second SMB signals between the SMB input and the second SMB output during the power mode.

### Claim 7 (depends on 4)

The PMIC of claim 4, wherein:
the first SMB output is configured to be coupled to a memory controller of a solid state device (SSD) memory sub-system; and
the second SMB output is configured to be coupled to a microcontroller of the SSD memory sub-system.

### Claim 8 (depends on 4)

The PMIC of claim 4, wherein a third SMB controller is configured to isolate the SMB input from a third SMB output of the multiple SMB outputs.

### Claim 9 (depends on 1)

The PMIC of claim 1, wherein the data is vital product data (VPD) that represents a health of a solid-state drive (SSD).

### Claim 10

A memory system comprising:
a memory component;
a power management integrated circuit (PMIC) comprising:
a system management bus (SMB) input; and
a hot swap SMB controller coupled to the SMB input, the hot swap SMB controller configured to route, based on a power mode, data between the SMB input and an SMB output of multiple SMB outputs.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein:
the PMIC further comprises power management circuitry configured to create a first power mode of the memory system; and
the PMIC is configured to isolate a memory controller of the memory component using the hot swap SMB controller and a first SMB controller during the first power mode.

### Claim 12 (depends on 11)

The memory system of claim 11, further comprising:
a host interface coupled to the SMB input of the PMIC; and
a microcontroller coupled to a second SMB output of the PMIC;
wherein the PMIC further comprises:
the second SMB output; and
a second SMB controller coupled to the hot swap SMB controller and the second SMB output.

### Claim 13 (depends on 12)

The memory system of claim 12, wherein the PMIC is configured to enable communications between the microcontroller and a host device via the host interface and the second SMB controller during the power mode.

### Claim 14 (depends on 12)

The memory system of claim 12, wherein:
the power management circuitry is further configured to create a second power mode;
the PMIC is configured to isolate the microcontroller using the second SMB controller during the second power mode; and
the PMIC is configured to enable SMB communications between a host device and the memory controller via the host interface and the first SMB controller during the second power mode.

### Claim 15 (depends on 10)

The memory system of claim 10, wherein the hot swap SMB controller is further configured to route address resolution protocol (ARP) communications between the SMB input and the multiple SMB outputs based on the power mode.

### Claim 16

A method comprising:
detecting, by power management circuitry of a power management integrated circuit (PMIC), a transition to a first power mode for a memory sub-system;
communicating, to a hot swap system management bus (SMB) controller of the PMIC, notification of the transition to the first power mode;
in response to the transition to the first power mode, connecting a first SMB output of the PMIC to an SMB input using the hot swap SMB controller and a first SMB controller connected to the first SMB output; and
routing, by the hot swap SMB controller, based on the memory sub-system being in the first power mode, data between the SMB input and the first SMB output.

### Claim 17 (depends on 16)

The method of claim 16, wherein the routing of the data between the SMB input and the first SMB output comprises:
relaying, from the SMB input to the first SMB output, a vital product data (VPD) request; and
relaying, from the first SMB output to the SMB input in response to the VPD request, a VPD response.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
detecting, by the power management circuitry of the PMIC, a transition to a second power mode different from the first power mode for the memory sub-system;
communicating, to the hot swap SMB controller of the PMIC, notification of the transition to the second power mode; and
in response to the transition to the second power mode:
isolating the first SMB output of the PMIC from the SMB input using the hot swap SMB controller and the first SMB controller; and
connecting a second SMB output of the PMIC to the SMB input using the hot swap SMB controller and a second SMB controller.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
relaying, from the SMB input to the second SMB output, a second VPD request while the memory sub-system is in the second power mode; and
relaying, from the second SMB output to the SMB input in response to the second VPD request, a second VPD response.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
configuring, by the hot swap SMB controller, the first SMB controller to communicate first SMB signals between the SMB input and the first SMB output during the first power mode; and
configuring the second SMB controller to communicate second SMB signals between the SMB input and the second SMB output during the second power mode.