# US 2021/0278868 A1 · Ldo overshoot protection

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0278868 A1
- Document ID: US20210278868A1
- Status: Published application
- Kind: A1
- Application number: 16/810,639
- Filed: 2020-03-05
- Published: 2021-09-09
- Earliest claimed: 2020-03-05
- Assignees: STMicroelectronics S.r.l.; STMicroelectronics (Rousset) SAS
- Applicants: STMicroelectronics S.r.l.; STMicroelectronics (Rousset) SAS
- Inventors: Michel Cuenca; Bruno Gailhard; Daniele Mangano
- Web page: https://patentgrep.com/patent/US20210278868A1

## CPC

- G05F 1/56: using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence)
- H02M 1/0045: {Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode}
- H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.

## Claims

### Claim 1

A method comprising:
receiving a main supply voltage;
generating a first regulated output voltage with a DC-DC converter;
providing the main supply voltage to a supply terminal of a driver of a control terminal of an output transistor of an LDO to power the driver, the LDO having an input terminal coupled to a first current path terminal of the output transistor, and an output terminal coupled to second current path terminal of the output transistor;
receiving, at the input terminal of the LDO, the first regulated output voltage;
generating, at the output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and
when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The method of claim 1, wherein the output transistor is a transistor of the p-type.

### Claim 4 (depends on 1)

The method of claim 1, wherein the predetermined threshold is substantially equal to a target regulation voltage of the LDO.

### Claim 5 (depends on 1)

The method of claim 1, wherein the DC-DC converter comprises a buck converter.

### Claim 6 (depends on 1)

The method of claim 1, wherein the driver is an error amplifier.

### Claim 7

A circuit comprising:
a DC-DC converter configured to receive a main supply voltage and to generate a first regulated output voltage from the main supply voltage;
an LDO comprising:
an input configured to receive the first regulated output voltage,
an output transistor having a current path coupled between the input of the LDO and an output of the LDO, and
an error amplifier having an output coupled to a control terminal of the output transistor, a first input configured to receive a reference voltage, a second input coupled to the output of the LDO, and a supply terminal configured to receive the main supply voltage to power the error amplifier, wherein the LDO is configured to generate a second regulated output voltage from the first regulated output voltage at the output of the LDO;
a capacitor coupled to the input of the LDO; and
a switch coupled to the input of the LDO and configured to discharge the capacitor when the main supply voltage falls below a predetermined threshold.

### Claim 8

(canceled)

### Claim 9 (depends on 7)

The circuit of claim 7, further comprising a digital core coupled to the current path of the output transistor.

### Claim 10 (depends on 7)

The circuit of claim 7, wherein the output transistor is a transistor of the p-type.

### Claim 11 (depends on 7)

The circuit of claim 7, further comprising a comparator having an input configured to receive the main supply voltage, and an output coupled to a control terminal of the switch.

### Claim 12 (depends on 7)

The circuit of claim 7, further comprising an analog-to-digital converter (ADC) having an input configured to receive the main supply voltage, wherein the switch is configured to discharge the capacitor based on an output of the ADC.

### Claim 13 (depends on 7)

The circuit of claim 7, wherein the predetermined threshold is substantially equal to a target regulation voltage of the LDO.

### Claim 14 (depends on 7)

The circuit of claim 7, wherein the DC-DC converter comprises a buck converter of the switched-mode power supply (SMPS) type.

### Claim 15 (depends on 7)

The circuit of claim 7, further comprising a load configured to receive the first regulated output voltage.

### Claim 16 (depends on 7)

The circuit of claim 7, wherein the DC-DC converter comprises the capacitor.

### Claim 17

A circuit comprising:
a main supply terminal configured to receive a main supply voltage;
a DC-DC converter having an input coupled to the main supply terminal and an output coupled to an intermediate supply terminal;
an LDO comprising:
an output transistor having a current path coupled between the intermediate supply terminal and an output terminal of the LDO, and
an error amplifier having an output coupled to a control terminal of the output transistor, a supply terminal coupled to the main supply terminal and configured to receive the main supply voltage for powering the error amplifier, a first input coupled to the output terminal of the LDO, and a second input;
a capacitor coupled to the intermediate supply terminal; and
a switch coupled to the intermediate supply terminal and configured to discharge the capacitor when the main supply voltage falls below a predetermined threshold.

### Claim 18

(canceled)

### Claim 19 (depends on 17)

The circuit of claim 17, further comprising a comparator having an input coupled to the main supply terminal, and an output coupled to a control terminal of the switch.

### Claim 20 (depends on 19)

The circuit of claim 19, wherein the comparator comprises a second input configured to receive the predetermined threshold, wherein the predetermined threshold is based on a target regulation voltage of the LDO.

### Claim 21 (depends on 17)

The circuit of claim 17, wherein the first input of the error amplifier is directly connected to the current path of the output transistor.

### Claim 22 (depends on 1)

The method of claim 1, wherein the predetermined threshold is lower than a target regulation voltage of the LDO.

### Claim 23 (depends on 1)

The method of claim 1, wherein the first regulated output voltage is lower than the main supply voltage, and wherein the second regulated output voltage is lower than the first regulated output voltage.