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US 2021/0272954 A1Published application
Self restoring logic structures
AssigneeICs LLC
InventorsSterling Whitaker, Gary Maki
Life of this patent
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AssigneeICs LLC
InventorsSterling Whitaker, Gary Maki
Estimating the term…
A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic. A SRL latch is formed of three NMOS and PMOS structures having a first latch with a first NMOS structure adjacent a first PMOS structure, a second latch with a second NMOS structure adjacent a second PMOS structure wherein the first and second NMOS structures are adjacent one another, and a third latch with a third NMOS structure adjacent a third PMOS structure wherein the second and third PMOS structures are adjacent one another, wherein the latch is adapted to have alternating logic with a state assignment of 010 and 101. A Single Event Upset Triple Modular Redundancy (TMR) tolerant circuit generates complementary output values 010 and 101 with layouts that are adjacent.
A logic structure comprising both NMOS and PMOS having two logic sections such that a first section having first logic circuits coupled to generate a first output signal having a first logic value and a second section having second logic circuits coupled to generate a second output signal that is a complement of the first logic signal and further wherein a fault to one section will be corrected by feedback from the output signal stored in the other section.
A Self Restoring Logic (SRL) latch formed of three NMOS and PMOS structures having a first latch with a first NMOS structure adjacent a first PMOS structure, a second latch with a second NMOS structure adjacent a second PMOS structure wherein the first and second NMOS structures are adjacent one another, and a third latch with a third NMOS structure adjacent a third PMOS structure wherein the second and third PMOS structures are adjacent one another, wherein the latch is adapted to have alternating logic with a state assignment of 010 and 101.
A logic structure formed of three NMOS and PMOS structures having a first circuit with a first NMOS structure adjacent a first PMOS structure, a second circuit with a second NMOS structure adjacent a second PMOS structure wherein the first and second NMOS structures are adjacent one another, and a third circuit with a third NMOS structure adjacent a third PMOS structure wherein the second and third PMOS structures are adjacent one another, wherein the latch is adapted to have alternating logic with a state assignment of 010 and 101.
A Single Event Upset Triple Modular Redundancy (TMR) tolerant circuit generates complementary output values from layouts that are adjacent.
A Single Event Upset (SEU) fault tolerant NMOS and PMOS combinational logic structure having a first circuit with a first NMOS structure adjacent a first PMOS structure to form a first logic section, a second circuit with a second NMOS structure adjacent to a second PMOS structure to form a second logic section wherein the first and second NMOS structures are adjacent one another, and a third circuit with a third NMOS structure adjacent a third PMOS structure to form a third logic section wherein the second and third PMOS structures are adjacent one another, wherein the combinational logic structure is adapted to have alternating logic with 010 and 101, further wherein outputs of the first and third logic sections are the same and the output of the second logic is the logical complement of the outputs of the first and third logic sections and wherein adjacent NMOS or PMOS regions contain no logic inversions.
Dependencies are inferred from the claim text.