US 2021/0265504 A1 · MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

Abstract

A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.

Claims14

Dependent claims

A semiconductor device comprising:

first to fourth wirings;
and
first and second transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein each of the first and second transistors is an n-channel transistor, and
wherein the first transistor comprises a metal oxide in a channel formation region.

7 more elements

A memory device comprising:

a memory cell array;
and
a peripheral circuit,
wherein the memory cell array comprises m×n (each of m and n is an integer greater than or equal to 1) memory cells, n first wirings, n second wirings, m third wirings, and m fourth wirings,
wherein the m×n memory cells are arranged in a matrix,
wherein each of the memory cells is electrically connected to the first to fourth wirings,
wherein each of the memory cells comprises first and second transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein each of the first transistor and the second transistor is an n-channel transistor,
wherein each of the first transistor and the second transistor comprises a metal oxide in a channel formation region,
wherein the peripheral circuit comprises a first circuit, a second circuit, and a controller,
wherein the first circuit is electrically connected to the first wiring and the second wiring,
wherein the first circuit is configured to write data to the memory cell and is configured to read data from the memory cell,
wherein the second circuit is electrically connected to the third wiring and the fourth wiring,
wherein the second circuit is configured to drive the third wiring and the fourth wiring, and
wherein the controller is configured to control the first circuit and the second circuit.

17 more elements

A memory device comprising:

a memory cell array;
and
a peripheral circuit,
wherein the memory cell array comprises m×n (each of m and n is an integer greater than or equal to 1) memory cells, n first wirings, n second wirings, m third wirings, and m fourth wirings,
wherein the m×n memory cells are arranged in a matrix,
wherein each of the memory cells is electrically connected to the first to fourth wirings,
wherein each of the memory cells comprises first and second transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein each of the first transistor and the second transistor is an n-channel transistor,
wherein each of the first transistor and the second transistor comprises a metal oxide in a channel formation region,
wherein the peripheral circuit comprises a first circuit, a second circuit, a controller, and a page buffer,
wherein the first circuit is electrically connected to the first wiring and the second wiring,
wherein the page buffer is configured to store data temporarily,
wherein the controller is configured to write data to the page buffer and is configured to read data from the page buffer,
wherein the first circuit is configured to write data read from the page buffer, to the memory cell and is configured to write data read from the memory cell, to the page buffer,
wherein the second circuit is electrically connected to the third wiring and the fourth wiring,
wherein the second circuit is configured to drive the third wiring and the fourth wiring,
wherein the controller is configured to control the first circuit and the second circuit, and
wherein the controller is configured to be a serial peripheral interface.

20 more elements

Dependencies are inferred from the claim text.

Memory device, semiconductor device, and electronic device

Life of this patent

Memory device, semiconductor device, and electronic device

Life of this patent

Abstract

Claims14