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US 2021/0265482 A1Published application
Gate electrode having a capping layer
AssigneeIntel Corporation
InventorsGilbert DEWEY, Mark L. DOCZY, Suman DATTA, Justin K. BRASK, Matthew V. METZ
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Abstract
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
Claims20
An integrated circuit structure, comprising:
- a semiconductor body having a top and a pair of laterally opposite sidewalls, the semiconductor body comprising germanium;
- a gate stack adjacent to the top and the pair of laterally opposite sidewalls of the semiconductor body comprising germanium, the gate stack comprising:
- a gate dielectric region, the gate dielectric region comprising hafnium and oxygen;
- a first region comprising nitrogen and silicon, wherein the gate dielectric region is between the first region and the semiconductor body;
- and
- a second region comprising aluminum and titanium, wherein the first region is between the second region and the gate dielectric region;
- a first source or drain region in the semiconductor body at a first side of the gate stack;
- and
- a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.
6 more elements
A method for forming an integrated circuit structure, comprising:
- forming a semiconductor body having a top and a pair of laterally opposite sidewalls, the semiconductor body comprising germanium;
- forming a gate stack adjacent to the top and the pair of laterally opposite sidewalls of the semiconductor body comprising germanium, forming the gate stack comprising:
- forming a gate dielectric region, the gate dielectric region comprising hafnium and oxygen;
- forming a first region comprising nitrogen and silicon, wherein the gate dielectric region is between the first region and the semiconductor body;
- forming a sacrificial layer, the sacrificial layer comprising polysilicon;
- removing the sacrificial layer;
- and
- forming a second region comprising aluminum and titanium, wherein the first region is between the second region and the gate dielectric region;
- forming a first source or drain region in the semiconductor body at a first side of the gate stack;
- and
- forming a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.
8 more elements
An integrated circuit structure, comprising:
- an insulating layer;
- a semiconductor body having a top and a pair of laterally opposite sidewalls, the semiconductor body comprising germanium, and the semiconductor body directly on the insulating layer;
- a gate stack adjacent to the top and the pair of laterally opposite sidewalls of the semiconductor body comprising germanium, wherein a portion of the gate stack is vertically over the insulating layer, the gate stack comprising:
- a gate dielectric region, the gate dielectric region comprising hafnium and oxygen;
- a first region comprising nitrogen and silicon, wherein the gate dielectric region is between the first region and the semiconductor body;
- and
- a second region comprising aluminum and titanium, wherein the first region is between the second region and the gate dielectric region;
- a first source or drain region in the semiconductor body at a first side of the gate stack;
- and
- a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.
7 more elements
Dependencies are inferred from the claim text.