Silicon Carbide Semiconductor Device
AssigneeInfineon Technologies AG
InventorsAndreas Huerner, Dethard Peters
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Abstract
A silicon carbide semiconductor device includes a first load electrode disposed on a first surface of a silicon carbide semiconductor body, a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode, and an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor including a source region and a body region, the body region being electrically connected to the first load electrode, wherein a geometry and dopant concentration of the first doped region is such that a resistance of the first doped region increases by at least a factor of two as load current in the insulated gate field effect transistor rises.
Claims12
A silicon carbide semiconductor device, comprising:
- a first load electrode disposed on a first surface of a silicon carbide semiconductor body;
- a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode;
- and
- an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor comprising a source region and a body region, the body region being electrically connected to the first load electrode,
- wherein a geometry and dopant concentration of the first doped region is such that a resistance of the first doped region increases by at least a factor of two as load current in the insulated gate field effect transistor rises.
A silicon carbide semiconductor device, comprising:
- a first load electrode disposed on a first surface of a silicon carbide semiconductor body;
- a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode;
- an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor comprising a source region and a body region, the body region being electrically connected to the first load electrode;
- a second doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode,
- wherein the second doped region forms a p-n junction with the first doped region, and wherein a depletion region extending from the p-n junction increases a resistance of the first doped region by at least a factor of two as load current in the insulated gate field effect transistor rises.
Dependencies are inferred from the claim text.