US 2021/0265456 A1 · DISPLAY PANEL

Abstract

The present disclosure provides a display panel. In order to reduce a parasitic capacitance that may occur between a data line and a semiconductor layer and a crosstalk caused by the parasitic capacitance, a display panel includes a substrate, a driving thin film transistor on the substrate, including a driving semiconductor layer and a driving gate electrode, a compensation thin film transistor on the substrate, including a compensation semiconductor layer and a compensation gate electrode, a node connection line electrically connecting the driving thin film transistor to the compensation thin film transistor, a scan line extending in a first direction on the substrate, and a gate connection line electrically connected to the scan line, which includes the compensation gate electrode, wherein the compensation semiconductor layer is closer to the driving semiconductor layer than the scan line when viewed on a plane.

Claims20

Dependent claims

A display panel comprising:

a substrate;
a driving thin film transistor disposed on the substrate, the driving thin film transistor including a driving semiconductor layer and a driving gate electrode;
a compensation thin film transistor disposed on the substrate, the compensation thin film transistor including a compensation semiconductor layer and a compensation gate electrode;
a node connection line electrically connecting the driving thin film transistor to the compensation thin film transistor;
a scan line extending in a first direction on the substrate;
and
a gate connection line electrically connected to the scan line, the gate connection line including the compensation gate electrode,
wherein the compensation semiconductor layer is disposed closer to the driving semiconductor layer than the scan line when viewed on a plane.

5 more elements

Dependencies are inferred from the claim text.

Display panel

Life of this patent

Display panel

Life of this patent

Abstract

Claims20