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US 2021/0265418 A1Published application
Monolithic led array and a precursor thereto
AssigneePlessey Semiconductors Limited
InventorsAndrea Pinos, Samir Mezouari
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Abstract
The present invention provides a monolithic LED array precursor comprising a plurality of LED structures, an LED device comprising the monolithic LED array, and a method of manufacture thereof. In particular, the present disclosure provides a monolithic LED array having improved light emission.
Claims20
A monolithic LED array precursor comprising:
- a plurality of LED structures sharing a first semiconductor layer, wherein the first semiconductor layer defines a plane of the LED array precursor, each LED structure comprising:
- (i) a second semiconductor layer on the first semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the second semiconductor layer has sloped sides;
- (ii) a third semiconductor layer on the second semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the third semiconductor layer has sloped sides parallel to the sloped sides of the second semiconductor layer;
- (iii) a fourth semiconductor layer on the third semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the fourth semiconductor layer has sloped sides parallel to the sloped sides of the third semiconductor layer;
- and
- (iv) a primary electrical contact on the fourth semiconductor layer, wherein the contact is only on the upper surface portion of the fourth semiconductor layer which is parallel to the plane of the LED array precursor;
- wherein the third semiconductor layer comprises a plurality of quantum well sub-layers, the quantum well sub-layers having a greater thickness on a portion parallel to the plane of the LED array precursor and a reduced thickness on a portion which is not parallel to the plane of the LED array precursor.
4 more elements
A method of forming a monolithic LED array precursor, the method comprising:
- (i) providing a substrate having a surface;
- (ii) forming a continuous first semiconductor layer on the surface of the substrate;
- (iii) selectively masking the first semiconductor layer, by depositing a masking layer, which comprises a plurality of apertures, on the first semiconductor layer;
- (iv) growing a second semiconductor layer on unmasked portions of the first semiconductor layer, through the apertures of the masking layer to form a plurality of columns each having a regular trapezoidal cross-section normal to the substrate and a substantially flat upper surface portion;
- (v) forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer comprises one or more quantum well sub-layers and has a substantially flat upper surface portion;
- (vi) forming a fourth semiconductor layer covering the third semiconductor layer, whereby the fourth semiconductor layer has a substantially flat upper surface portion;
- (vii) forming primary electrical contacts on the substantially flat upper surface portion of the fourth semiconductor layer;
- and
- wherein the first to fourth semiconductor layers comprise Group III-nitrides.
6 more elements
A method of forming a monolithic LED array precursor, the method comprising:
- (i) providing a substrate having a surface;
- (ii) forming a continuous first semiconductor layer on the surface of the substrate;
- (iii) selectively treating the first semiconductor layer to form an amorphous surface pattern, wherein the amorphous surface pattern defines a plurality of untreated portions of the first semiconductor layer;
- (iv) growing a second semiconductor layer on the untreated portions of the first semiconductor layer to form a plurality of columns each having a regular trapezoidal cross-section normal to the substrate and a substantially flat upper surface portion;
- (v) forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer comprises one or more quantum well sub-layers and has a substantially flat upper surface portion;
- (vi) forming a fourth semiconductor layer covering the third semiconductor layer, whereby the fourth semiconductor layer has a substantially flat upper surface portion;
- and
- (vii) forming primary electrical contacts on the substantially flat upper surface portion of the fourth semiconductor layer wherein the first to fourth semiconductor layers comprise Group III-nitrides.
5 more elements
(canceled)
Dependencies are inferred from the claim text.