Vertical memory devices

A vertical memory device, comprising:

• a substrate including a memory cell region and a pad region surrounding the memory cell region;
• a conductive path disposed on the memory cell region, the conductive path including conductive patterns that are spaced apart from each other in a first direction that is substantially perpendicular to an upper surface of the substrate, wherein the conductive path extends in at least one of second and third directions that are substantially parallel to the upper surface of the substrate and cross each other;
• and
• shared memory blocks disposed on cell array regions, respectively, of the substrate, the cell array regions are portions of the memory cell region of the substrate that are spaced apart from each other by the conductive path,
• wherein each of the shared memory blocks includes memory blocks arranged in the third direction on each of the cell array regions of the substrate, the memory blocks are divided by a first division pattern extending in the second direction,
• wherein each of the memory blocks includes:
• horizontal gate electrodes disposed on the substrate and spaced apart from each other in the first direction, each of the horizontal gate electrodes extending in the second direction;
• vertical channels each extending through the horizontal gate electrodes in the first direction;
• and
• charge storage structures, wherein each of the charge storage structures are disposed between each of the vertical channels and the horizontal gate electrodes, and
• the horizontal gate electrodes at each level of the memory blocks in each of the shared memory blocks are electrically connected to the conductive path at a first lateral side in the second direction or a second lateral side in the third direction of each of the shared memory blocks and are configured to be shared by the shared memory blocks.

A vertical memory device, comprising:

• a substrate including a first region and a second region;
• first pass transistors disposed on the second region of the substrate;
• second and third pass transistors disposed on the first region of the substrate;
• first, second and third lower circuit patterns disposed on the substrate, the first to third lower circuit patterns are configured to be electrically connected to the first to third pass transistors, respectively;
• a common source plate (CSP) disposed on the first to third lower circuit patterns;
• memory blocks each including:
• first, second and third horizontal gate electrodes disposed on the CSP, the first, second and third horizontal gate electrodes are spaced apart from each other in a first direction that is substantially perpendicular to an upper surface of the substrate, wherein each of the first to third horizontal gate electrodes extends on the first and second regions of the substrate in a second direction that is substantially parallel to the upper surface of the substrate;
• vertical channels disposed on the first region, each of the vertical channels extends through the first to third horizontal gate electrodes in the first direction;
• and
• charge storage structures disposed on sidewalls of the vertical channels, respectively;
• a conductive path extending on the substrate in a third direction that is substantially parallel to the upper surface of the substrate and crosses the second direction;
• a first switching transistor configured to control electrical signals applied to the second horizontal gate electrodes, the first switching transistor is disposed on the first region of the substrate and includes;
• a first vertical gate electrode extending through the first to third horizontal gate electrodes in the first direction on the first region of the substrate, the first vertical gate electrode is electrically insulated from the first to third horizontal gate electrodes;
• and
• a first horizontal channel disposed at a portion of each of the second horizontal gate electrodes that is adjacent to the first vertical gate electrode;
• and
• a second switching transistor configured to control electrical signals applied to the third horizontal gate electrode, the second switching transistor is disposed on the first region of the substrate and includes;
• a second vertical gate electrode extending through the first to third horizontal gate electrodes in the first direction on the first region of the substrate, the second vertical gate electrode is electrically insulated from the first to third horizontal gate electrodes and is spaced apart from the first vertical gate electrode in the second direction;
• and
• a second horizontal channel disposed at a portion of the third horizontal gate electrodes that is adjacent to the third vertical gate electrodes,
• wherein the memory blocks are disposed in the third direction, and divided by a division pattern that extends in the second direction, the first, second and third horizontal gate electrodes at each level of the memory blocks are connected to form a shared memory block, and
• wherein the first, second and third horizontal gate electrodes at each level included in the shared memory block are connected to the conductive path at a lateral side in the second direction of the shared memory block.