Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same

A three-dimensional memory device, comprising:

• a source contact layer located over a substrate and comprising a doped semiconductor material;
• an alternating stack of insulating layers and electrically conductive layers located over the source contact layer;
• memory openings vertically extending through the alternating stack and the source contact layer;
• and
• memory opening fill structures located in the memory openings,
• wherein each of the memory opening fill structures comprises:
• a memory film including a first tubular portion that vertically extends through the alternating stack;
• a semiconductor channel contacting an inner sidewall of the memory film;
• a source region adjoined to a bottom end of the semiconductor channel and contacting the source contact layer;
• a dielectric pillar laterally surrounded by the source region;
• and
• a dielectric core laterally surrounded by a vertically-extending portion of the semiconductor channel and vertically spaced from the dielectric pillar by a bottom portion of the semiconductor channel.