Embedded pad structures of three-dimensional memory devices

A 3D memory device, comprising:

• an array interconnect layer disposed over an alternating conductor/dielectric stack;
• a pad and a first array interconnect structure both embedded in the array interconnect layer and electrically connected with each other;
• and
• a peripheral interconnect layer disposed over a first peripheral device and including a first peripheral interconnect structure;
• wherein the array interconnect layer is bonded with the peripheral interconnect layer, such that the first array interconnect structure is in electrical contact with the first peripheral interconnect structure, and the pad is electrically connected with the first peripheral device through the first array interconnect structure and the first peripheral interconnect structure.

A 3D memory device, comprising:

• a pad disposed beside an alternating conductor/dielectric stack;
• an array interconnect layer disposed over the alternating conductor/dielectric stack and the pad;
• a first array interconnect structure embedded the array interconnect layer and electrically connected with the pad;
• and
• a peripheral interconnect layer disposed over a first peripheral device and including a first peripheral interconnect structure;
• wherein the array interconnect layer is bonded with the peripheral interconnect layer, such that the first array interconnect structure is in electrical contact with the first peripheral interconnect structure, and the pad is electrically connected with the first peripheral device through the first array interconnect structure and the first peripheral interconnect structure.