Non-volatile memory device and manufacturing method thereof

A non-volatile memory device, comprising:

• a substrate;
• at least one first doping region formed in the substrate;
• a plurality of stacked structures formed on the substrate and connected in series with each other via the at least one first doping region, wherein each of the stacked structures comprises:
• a floating gate;
• a select logic gate disposed on the floating gate;
• a logic gate dielectric layer disposed between the floating gate and the substrate;
• and
• an inter-polysilicon layer dielectric layer disposed between the floating gate and the select logic gate;
• a plurality of second doping regions formed in the substrate at one side of the floating gate, wherein a channel region is formed between one of the second doping regions and the at least one first doping region;
• a plurality of anti-fuse gates disposed on the substrate and connected in series with one of the stacked structures via one of the second doping regions;
• and
• a gate dielectric layer disposed between each of the anti-fuse gates and the substrate.

A method for manufacturing a non-volatile memory device, comprising:

• forming a logic gate dielectric layer on a substrate;
• forming a first conductor layer on the logic gate dielectric layer;
• patterning the first conductor layer and the logic gate dielectric layer to form at least one floating gate and at least one anti-fuse gate;
• forming a first doping region and a second doping region in the substrate at two sides of the floating gate, wherein the second doping region is located between the floating gate and the anti-fuse gate to connect the floating gate with the anti-fuse gate in series;
• forming an inter-polysilicon layer dielectric layer over the substrate to cover the floating gate and the anti-fuse gate;
• forming a second conductor layer on the inter-polysilicon layer dielectric layer;
• and
• patterning the second conductor layer and the inter-polysilicon layer dielectric layer to form a select logic gate located on the floating gate, wherein the select logic gate, the inter-polysilicon layer dielectric layer, the floating gate, and the logic gate dielectric layer form a stacked structure.