Embedded ferroelectric finfet memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsBo-Feng Young, Chung-Te Lin, Sai-Hooi Yeong, Yu-Ming Lin, Sheng-Chih Lai, Chih-Yu Chang, Han-Jong Chia
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Abstract
Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.
Claims20
A ferroelectric memory device, comprising:
- a pair of source/drain regions disposed in a substrate;
- a gate dielectric disposed over the substrate and between the source/drain regions;
- a gate electrode disposed on the gate dielectric;
- a polarization switching structure disposed on the gate electrode;
- and
- a pair of sidewall spacers disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.
An integrated chip (IC), comprising:
- a logic region and a memory region integrated in a substrate;
- a logic device disposed in the logic region and comprising a logic device gate stack disposed over the substrate;
- a ferroelectric FinFET memory device disposed in the memory region and comprising a memory device gate stack over the substrate and a polarization switching structure disposed on the memory device gate stack;
- a first self-aligned contact (SAC) mask disposed on the logic device gate stack and the memory device gate stack and adjacent to the polarization switching structure;
- and
- a sidewall spacer disposed along sidewalls of the memory device gate stack, the polarization switching structure, and the first SAC mask.
A method of forming a ferroelectric FinFET memory device, comprising:
- forming an initial gate stack comprising a gate dielectric over a substrate and a sacrificial gate over the gate dielectric;
- forming a sidewall spacer over the substrate and along sides of the initial gate stack;
- removing and replacing the sacrificial gate by a metal gate;
- recessing the metal gate to form a recessed space between an upper portion of the sidewall spacer;
- forming a self-aligned contact (SAC) mask in the recessed space;
- forming an opening through the SAC mask that exposing the metal gate;
- and
- filling the opening with a polarization switching structure.
Dependencies are inferred from the claim text.