Integrated Memory Having Non-Ohmic Devices and Capacitors

A memory cell comprising:

• a transistor having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions;
• and
• a capacitor electrically coupled to the second source/drain region through a non-ohmic device that is a non-memory element in operation;
• the non-ohmic device including a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region.

A memory array, comprising:

• digit lines extending along a first direction;
• access transistors having first source/drain regions electrically coupled with the digit lines;
• wordlines operatively proximate the channel regions and extending along a second direction that crosses the first direction;
• and
• capacitors electrically coupled with the second source/drain regions through non-ohmic devices that are non-memory elements;
• the capacitors being comprised by memory cells;
• each of the memory cells being uniquely addressed by one of the digit lines in combination with one of the wordlines.