Low Leakage Device

A semiconductor device, comprising:

• a first plurality of gate-all-around (GAA) devices in a first device area, wherein each of the first plurality of GAA devices comprises:
• a first vertical stack of channel members extending along a first direction,
• a first gate top feature disposed over a topmost channel member of the first vertical stack of channel members, and
• a plurality of first lower gate features disposed between two adjacent channel members of the first vertical stack of channel members;
• and
• a second plurality of GAA devices in a second device area, wherein each of the second plurality of GAA devices comprises:
• a second vertical stack of channel members extending along a second direction,
• a second gate top feature disposed over a topmost channel member of the second vertical stack of channel members, and
• a plurality of second lower gate features disposed between two adjacent channel members of the second vertical stack of channel members,
• wherein the first gate top feature comprises a first length along the first direction,
• wherein the second gate top feature comprises a second length along the second direction,
• wherein the first length and the second length are substantially identical,
• wherein each of the plurality of first lower gate features comprises a third length along the first direction,
• wherein each of the plurality of second lower gate features comprises a fourth length along the second direction,
• wherein the third length is greater than the fourth length.

A semiconductor structure, comprising:

• a first transistor comprising:
• a first source/drain feature and a second source/drain feature,
• a first plurality of nanostructures extending between the first source/drain feature and the second source/drain feature along a direction, and
• a first gate structure wrapping around each of the first plurality of nanostructures;
• and
• a second transistor comprising:
• a third source/drain feature and a fourth source/drain feature,
• a second plurality of nanostructures extending between the third source/drain feature and the fourth source/drain feature along the direction, and
• a second gate structure wrapping around each of the second plurality of nanostructures,
• wherein each of the first source/drain feature and the second source/drain feature comprises a first thickness along the direction,
• wherein each of the third source/drain feature and the fourth source/drain feature comprises a second thickness along the direction,
• wherein the second thickness is greater than the first thickness.