Semiconductor device in a level shifter with electrostatic discharge (esd) protection circuit and semiconductor chip
AssigneeMagnaChip Semiconductor, Ltd.
InventorsKyong Jin HWANG, Hyun Kwang JEONG
Life of this patent
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Abstract
The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.
Claims20
A semiconductor device, comprising:
- a source region and a drain region formed in a substrate;
- a gate dielectric layer comprising a thin gate dielectric layer and a thick gate dielectric layer formed on the substrate;
- a gate electrode formed on the gate dielectric layer and electrically connected to a gate protection region;
- a silicide layer formed on the source region, drain region, and gate contact regions connected to the gate protection region;
- and
- a silicide blocking layer configured to prevent silicide formation and formed on the gate protection region,
- wherein the gate electrode and the gate protection region each comprise a polysilicon layer, and
- wherein the gate protection region has a higher resistance per unit area than that of the gate electrode.
A semiconductor device, comprising:
- a substrate having an active region and an isolation region;
- a gate dielectric layer comprising a thin gate dielectric layer and a thick gate dielectric layer formed on the substrate;
- a source region disposed adjacent to the thin gate dielectric layer, and a drain region disposed adjacent to the thick gate dielectric layer;
- a well region of a first conductivity type and an extended drain junction region of a second conductivity type formed in the well region;
- a gate electrode formed on the gate dielectric layer and electrically connected to a gate protection region;
- and
- a silicide layer formed on the source region, drain region, and gate contact regions connected to the gate protection region,
- wherein the gate electrode and the gate protection region each comprise a polysilicon layer,
- wherein the gate protection region has a higher resistance per unit area than that of the gate electrode, and
- wherein the extended drain junction region overlaps with the gate electrode and extends to a portion of the well region under the thin gate dielectric layer.
Dependencies are inferred from the claim text.