Semiconductor cell blocks having non-integer multiple of cell heights

A computer-implemented method of generating a layout for a semiconductor cell block, the computer-implemented method comprising:

• placing, with a placement and routing tool, a first semiconductor cell in a first layer of a stack of layers and a second semiconductor cell in a second layer of the stack of layers, the first semiconductor cell having a first cell height and the second semiconductor cell having a second cell height larger than the first height, the second cell height being a non-integer value multiple of the first cell height;
• placing, with the placement and routing tool, pins on each of the first semiconductor cell and the second semiconductor cell;
• placing, with the placement and routing tool, vias connected to the pins;
• and
• placing, with the placement and routing tool, metal routing layers connected to the vias.