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US 2021/0265333 A1Published application
High density architecture design for 3d logic and 3d memory circuits
AssigneeTokyo Electron Limited
InventorsMark I. Gardner, H. Jim Fulford
Life of this patent
Estimating the term…
Abstract
Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with 3D NAND devises are fabricated on a first wafer, and high voltage and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.
Claims20
A method of forming a circuit, the method comprising:
- on a first substrate that has a front side opposite a backside, forming a first layer of low-voltage and high-voltage devices on the front side, forming first memory devices on the first layer of low-voltage and high-voltage devices, and forming a first wiring plane above the first memory devices:
- on a second substrate that has a front side opposite a backside, forming a second layer of low-voltage and high-voltage devices on the front side, forming second memory devices on the second layer of low-voltage and high-voltage devices, and forming a second wiring plane above the second memory devices;
- and
- aligning the first wiring plane to be in contact with the second wiring plane and joining the first substrate with the second substrate to form a combined substrate.
1 more element
A method of forming a circuit, the method comprising:
- on a first substrate that has a front side opposite a backside, forming a layer of low-voltage and high-voltage devices on the front side, forming memory devices on the layer of low-voltage and high-voltage devices, and forming a first wiring plane above the memory devices;
- on a second substrate that has a front side opposite a backside, forming a layer of 3D SRAM and 3D Logic devices on the front side, and forming a second wiring plane above the layer of 3D SRAM and 3D Logic devices;
- and
- aligning the first wiring plane to be in contact with the second wiring plane and joining the first substrate with the second substrate to form a combined substrate.
1 more element
A method of forming a circuit, the method comprising:
- on a first substrate that has a front side opposite a backside, forming a layer of 3D SRAM and 3D Logic devices on the front side, and forming a first wiring plane above the layer of 3D SRAM and 3D Logic devices;
- on a second substrate that has a front side opposite a backside, forming a layer of microprocessor and 3D SRAM devices on the front side, and forming a second wiring plane above the layer of microprocessor and 3D SRAM devices;
- and
- aligning the first wiring plane to be in contact with the second wiring plane and joining the first substrate with the second substrate to form a combined substrate.
1 more element
Dependencies are inferred from the claim text.