Package and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Wei Wu, Szu-Wei Lu, Ying-Ching Shih
Life of this patent
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Abstract
A package includes at least one memory component and an insulating encapsulation. The at least one memory component includes a stacked memory structure and a plurality of conductive posts. The stacked memory structure is laterally encapsulated in a molding compound. The conductive posts are disposed on an upper surface of the stacked memory structure. The upper surface of the stacked memory structure is exposed from the molding compound. The insulating encapsulation encapsulates the at least one memory component. The top surfaces of the conductive posts are exposed form the insulating encapsulation. A material of the molding compound is different a material of the insulating encapsulation.
Claims20
A package, comprising:
- at least one memory component, including a stacked memory structure laterally encapsulated in a molding compound and a plurality of conductive posts, disposed on an upper surface of the stacked memory structure, and the upper surface of the stacked memory structure is exposed from the molding compound;
- and
- an insulating encapsulation, encapsulating the at least one memory component, wherein top surfaces of the plurality of conductive posts are exposed from the insulating encapsulation, and a material of the molding compound is different from a material of the insulating encapsulation.
A package, comprising;
- a first insulating encapsulation;
- at least one memory component, encapsulated in the first insulating encapsulation, wherein the at least one memory component comprises a stacked memory structure molded in a molding compound, wherein the first insulating encapsulation comprises a covering portion and a side wall portion, the covering portion overlaying an upper surface of the stacked memory structure, and the side wall portion surrounds sidewalls of the at least one memory component;
- a second insulating encapsulation, encapsulating the at least one memory component and exposing the covering portion of the first insulating encapsulation, wherein the first insulating encapsulation is sandwiched between the second insulating encapsulation and the molding compound;
- a semiconductor chip structure, embedded in the second insulating encapsulation and arranged aside the at least one memory component;
- and
- a redistribution structure, overlaying and electrically connected to the at least one memory component and the semiconductor chip structure.
A manufacturing method of a package, comprising:
- providing a carrier and disposing first and second memory components on the carrier, wherein the first memory component has a thickness different from a thickness of the second memory component;
- encapsulating the first and second memory components with a first encapsulation material;
- planarizing the first encapsulation material to form a first insulating encapsulation, to make the thickness of the first memory component substantially equal with the thickness of the second memory component with backsides of the first and second memory components exposed;
- cutting through the first insulating encapsulation to separate first die units including the first and/or second memory components encapsulated therein;
- disposing the first die units alongside second die units;
- encapsulating the first and second die units with a second encapsulation material, wherein the second encapsulation material is different from the first encapsulation material;
- planarizing the second encapsulation material to form a second insulating encapsulation and expose the first and second die units;
- and
- forming a redistribution structure over the second insulating encapsulation and the first and second die units to electrically connect the first and second die units.
Dependencies are inferred from the claim text.