Dram memory device with xtacking architecture
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsLei LIU, Di WANG, Wenxi ZHOU, Zhiliang XIA
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Abstract
A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.
Claims20
A semiconductor device, comprising:
- a first wafer having an array transistor formed therein;
- a second wafer having a capacitor structure formed therein;
- and
- a bonding interface formed between the first wafer and the second wafer that includes a plurality of bonding structures that are configured to couple the array transistor to the capacitor structure to form a memory cell.
A method for manufacturing a semiconductor device, comprising:
- forming an array transistor in a first side of a first substrate;
- forming a first dielectric stack on a first side of a second substrate;
- and
- forming a capacitor structure in the first dielectric stack and over the first side of the second substrate;
- and
- bonding the first substrate and the second substrate through a plurality of bonding structures so that the capacitor structure is coupled to the array transistor, and the first side of the first substrate and the first side of the second substrate face to each other.
A semiconductor device, comprises:
- a first array region and a first periphery region formed over a first side of a first substrate, the first array region having at least one array transistor formed in the first side of the first substrate, the first periphery region having at least one periphery transistor formed in the first side of the first substrate;
- a second array region and a second periphery region formed over a first side of a second substrate, the second array region having at least one capacitor structure formed over the first side of the second substrate, the at least one capacitor structure being coupled to a first doped region of the at least one array transistor, the first side of the first substrate and the first side of the second substrate facing each other;
- and
- a plurality of bonding structures that are configured to bond the first substrate to the second substrate so that the first array region is coupled to the second array region, and the first periphery region is coupled to the second periphery region.
Dependencies are inferred from the claim text.