Back-end-of-line interconnect structures with varying aspect ratios

An integrated circuit comprising:

• a semiconductor structure comprising:
• an interlayer dielectric layer;
• a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer;
• and
• a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer;
• wherein each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio;
• and
• wherein each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio, the second width being greater than the first width, the second height being different than the first height.

A method of forming a semiconductor structure, comprising:

• forming a first set of back-end-of-line interconnect structures in an interlayer dielectric layer;
• and
• forming a second set of back-end-of-line interconnect structures at least partially in the interlayer dielectric layer;
• wherein each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio;
• and
• wherein each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio, the second width being greater than the first width, the second height being different than the first height.