Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• a core substrate having a first surface and a second surface opposite to each other, and having a through hole that extends from the first surface to the second surface;
• a first molding member having a first portion covering the first surface of the core substrate and a second portion covering an inner sidewall of the through hole, the second portion having a cavity within the through hole and exposed from the second surface of the core substrate;
• a first semiconductor chip on the first molding member on the first surface of the core substrate;
• a second semiconductor chip within the cavity of the first molding member;
• a second molding member on the first molding member on the first surface of the core substrate and covering the first semiconductor chip;
• a third molding member on the second surface of the core substrate, filling the cavity of the first molding member, and covering the second semiconductor chip;
• first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate;
• second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings of the core substrate;
• and
• a lower redistribution wiring layer on the third molding member and having lower redistribution wirings electrically connected to the second redistribution wirings, respectively.

A semiconductor package, comprising:

• a core substrate having a through hole;
• a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole and extending in a thickness direction from a lower surface of the core substrate;
• a first semiconductor chip on the first molding member on the upper surface of the core substrate;
• a second semiconductor chip within the cavity of the first molding member;
• a second molding member on the first molding member and covering the first semiconductor chip;
• a third molding member filling the cavity and covering the lower surface of the core substrate;
• first redistribution wirings on the second molding member, and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate;
• and
• second redistribution wirings on the third molding member, and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings of the core substrate.