3d nand memory device and method of forming the same

A method for fabricating a semiconductor device, comprising:

• forming an initial stack of sacrificial word line layers and insulating layers that are arranged alternately over a substrate of the semiconductor device;
• forming a first staircase in a first staircase region of a connection region of the initial stack, the first staircase having non-quadrilateral treads;
• and
• forming a second staircase in a second staircase region of the connection region of the initial stack, the second staircase having non-quadrilateral treads, wherein
• the connection region of the initial stack includes a separation region between the first staircase and the second staircase, and
• the connection region is positioned between two array regions at opposing sides of the initial stack.

A semiconductor device, comprising:

• a stack of word line layers and insulating layers that are stacked alternatingly over a substrate;
• a first array region and a second array region formed in the stack and further positioned at two opposing sides of the stack;
• one or more slit structures formed in the first array region and the second array region, the one or more slit structures extending from the substrate and further extending through the stack to separate the first array region and the second array region into sub-first array regions and sub-second array regions respectively;
• and
• a connection region formed in the stack and positioned between the first array region and the second array region, wherein:
• a first staircase is formed in the connection region of the stack that is arranged between the first array region and the second array region, the first staircase having non-quadrilateral treads;
• a second staircase is formed in the connection region of the stack, the second staircase having non-quadrilateral treads;
• and
• the connection region in the stack includes a separation region positioned between the first and second staircases.