Fabricating field-effect transistors with interleaved source and drain finger configuration

A method for fabricating a field-effect transistor (FET), the method comprising:

• providing a substrate;
• implementing a first assembly of source, gate, and drain on a first active region of the substrate;
• implementing a second assembly of source, gate, and drain implemented on a second active region of the substrate;
• forming a first body contact between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly;
• forming a finger configuration for the source, the gate, and the drain on each of the first assembly and the second assembly, each finger configuration including a plurality of fingers, the finger configuration of each of the first assembly and the second assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows;
• and
• electrically connecting a particular source finger of the first assembly to a source finger of the second assembly that is offset by one row from the particular source finger of the first assembly.

A method for fabricating a radio-frequency (RF) device, the method comprising:

• forming a field-effect transistor (FET) over a substrate layer, the FET including a first assembly of source, gate, and drain on a first active region of the substrate layer, the FET also including a second assembly of source, gate, and drain implemented on a second active region of the substrate layer, the FET also including a first body contact implemented between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly, the FET also including a finger configuration for the source, the gate, and the drain on each of the first assembly and the second assembly, each finger configuration including a plurality of fingers, the finger configuration of each of the first assembly and the second assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows;
• electrically connecting a particular source finger of the first assembly to a source finger of the second assembly that is positioned on the same row or that is offset by one row from the particular source finger of the first assembly;
• electrically connecting the substrate layer to a substrate node;
• and
• coupling a non-grounding circuit to the substrate node to adjust RF performance of the FET.