Front-end-of-line (feol) through semiconductor-on-substrate via (tsv)

An integrated circuit (IC) chip comprising:

• a substrate;
• a semiconductor layer overlying the substrate;
• a semiconductor device on the semiconductor layer;
• an interconnect structure overlying the semiconductor device;
• a contact extending from the interconnect structure to the semiconductor device;
• and
• a through via extending through the semiconductor layer to the substrate and having a top surface about even with, or recessed relative to, a top surface of the contact.

A method for forming an integrated circuit (IC) chip, the method comprising:

• depositing a semiconductor layer over a substrate;
• forming a semiconductor device on the semiconductor layer;
• forming a front-end-of-line (FEOL) layer over the semiconductor device;
• patterning the FEOL layer and the semiconductor layer to form a trench extending through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip;
• filling the trench with dielectric and/or conductive material(s) to form a through via;
• and
• forming an intermetal dielectric (IMD) layer over the through via and the FEOL layer while simultaneously forming an alternating stack of wires and vias in the IMD layer.