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US 2021/0265236 A1Published application
Chip Warpage Reduction Via Raised Free Bending & Re-entrant (Auxetic) Trace Geometries
AssigneeBoard of Trustees of the University of Arkansas
InventorsDavid Huitink, John Harris
Life of this patent
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Abstract
A microelectronic device and method of making the same including a substrate and at least one expansion layer that adds stress to the substrate when said substrate expands.
Claims10
A transformer comprising:
- a plurality of passive copper layers, each of said copper layers including an expansion layer thereon;
- and wherein when each of said passive copper layers expand, said expansion layers become thicker perpendicular to the direction of expansion.
A method of reducing the warpage of passive copper layers in a transformer comprising the steps of:
- forming an expansion layer on said passive copper layers wherein when said passive copper layers expand said expansion layers become thicker perpendicular to the direction of expansion.
Dependencies are inferred from the claim text.