Fuse array layout pattern and related apparatuses, systems, and methods
AssigneeMicron Technology, Inc.
InventorsWei Lu Chu, Jing Wang, Zhiwei Liang, Raghu Sreeramaneni
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AssigneeMicron Technology, Inc.
InventorsWei Lu Chu, Jing Wang, Zhiwei Liang, Raghu Sreeramaneni
Estimating the term…
Systems, methods, and apparatuses relating to interlocking transistor active regions are disclosed. An apparatus includes a gate including electrically conductive material and an active material including a doped semiconductor material. A portion of the active material overlapped by the gate has an at least substantially triangular shape. An apparatus includes a plurality of active materials. Each active material of includes tapered ends and a plurality of gates. The plurality of active materials is arranged in an interlocking pattern with at least some tapered ends of the active materials interlocking with at least some others of the tapered ends. The plurality of gates overlaps the interlocked tapered ends of the plurality of active materials.
An apparatus, comprising:
An apparatus, comprising:
A method of operating a fuse circuit, the method comprising:
A computing system comprising a fuse array including a plurality of fuse cells, the plurality of fuse cells comprising:
Dependencies are inferred from the claim text.