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US 2021/0264990 A1Published application
Semiconductor memory
AssigneeKioxia Corporation
InventorsNoboru SHIBATA, Hironori UCHIKAWA, Taira SHIBUYA
Life of this patent
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Abstract
A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.
Claims16
A semiconductor memory comprising:
- a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of at least eight different threshold voltage levels;
- a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of at least eight different threshold voltage levels;
- a first word line coupled to the first memory cell;
- a second word line coupled to the second memory cell;
- and
- a controller configured to read data of one of at least six bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell,
- wherein:
- the controller is configured to perform:
- a first read operation to read a first one of the at least six bits,
- a second read operation to read a second one of the at least six bits,
- a third read operation to read a third one of the at least six bits,
- a fourth read operation to read a fourth one of the at least six bits,
- a fifth read operation to read a fifth one of the at least six bits, and
- a sixth read operation to read a sixth one of the at least six bits,
- in the first read operation, the controller applies at least one type of read voltage to the first word line,
- in the second read operation, the controller applies at least one type of read voltage to the second word line, and
- in the third read operation, the controller applies at least one type of read voltage to the first word line, and applies at least one type of read voltage to the second word line.
14 more elements
A semiconductor memory comprising:
- a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels;
- a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels;
- a first word line coupled to the first memory cell;
- a second word line coupled to the second memory cell;
- and
- a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell,
- wherein:
- in a read operation to read one of the different bits, the controller applies at least one type of read voltage to the first word line,
- in a read operation to read another one of the different bits, the controller applies at least one type of read voltage to the second word line, and
- in a read operation to read still another one of the different bits, the controller applies at least one type of read voltage to the first word line, and applies at least one type of read voltage to the second word line.
7 more elements
A method for controlling a semiconductor memory, the semiconductor memory comprising:
- a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels;
- a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels;
- a first word line coupled to the first memory cell;
- a second word line coupled to the second memory cell;
- and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell, the method comprising:
- in a read operation to read one of the different bits, applying at least one type of read voltage to the first word line;
- in a read operation to read another one of the different bits, applying at least one type of read voltage to the second word line;
- and
- in a read operation to read still another one of the different bits, applying at least one type of read voltage to the first word line, and applying at least one type of read voltage to the second word line.
6 more elements
Dependencies are inferred from the claim text.